38 tagged rtl, measured the same way as everything else here.
Browse within: amba-apb 18amba-axi 18cocotb 18crossbar 18system-verilog 18verilog 11chip-design 10rtl-design 10systemverilog 10i18n 7ReAct 6boilerplate 6google-analytics 6sentry 6
Skill Claude CodeCodex
Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed…
Skill Claude CodeCodex
How to run a regression correctly - always "make clean-all && make run-all-{gate,func,full}-parallel", never a bare pytest. Use whenever running or re-running any test suite in val/ or projects/components/, or before reporting a suite as passing.
Skill Claude CodeCodex
External doc-review rounds (Kimi) - bundle building, serial dispatch, round protection, token budgets, findings triage (doc-fix vs RTL-fix), measuring integration status rather than trusting commit history, verifying fixes with clean rebuilds + mutation checks, and the humanization pass. Use when sending docs for…
Skill Claude CodeCodex
Where project tasks/TODOs live and how to track them - the /vault/Tasks/ / directory with open/active/deferred/closed/dropped lifecycle pages. Use whenever you would record a TODO, start/finish a task, or are tempted to create a TASKS.md or TODO.md next to code.
Skill Claude CodeCodex
Generate validated SVG block diagrams for HDL/RTL/FPGA/SoC designs. Use when asked to draw, diagram, sketch, render, or visualize Verilog, SystemVerilog, VHDL, Vivado BD, or LiteX architecture. Produces JSON specs plus SVGs, color-codes clock domains, distinguishes AXI/MM/Lite/Stream and TileLink, and hides…
cobbpeng/fpga-hardware-design-and-review-guide
Skill Claude CodeCodex
Comprehensive FPGA hardware design guide based on real-world project experience. Covers pipeline architecture, timing optimization, SystemVerilog coding patterns, CDC handling, and practical debugging techniques. Use this skill when: (1) designing FPGA modules with timing constraints, (2) implementing video processing…
Skill Claude CodeCodex
Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton.
Skill Claude CodeCodex
Generate a design proposal, documentation, and RTL backbone from a requirement file.
Skill Claude CodeCodex
Implement Verilog code from an approved design proposal, then lint and simulate.
kws-projects/react-boilerplate
Skill Claude CodeCodexCursor
Work with the GA4 analytics and Sentry error-monitoring integrations in this project. Use when adding events, capturing errors, configuring user identity, managing consent, or troubleshooting the integration.
kws-projects/react-boilerplate
Skill Claude CodeCodexCursor
Work with the design-token color system in this project. Use when adding, changing, or debugging colors, or when the user asks about theming, design tokens, OKLCH, or "how do I use colors".
kws-projects/react-boilerplate
Skill Claude CodeCodexCursor
Integrate or modify consent handling for GA4 Consent Mode v2. Use when launching in a consent-required market (EU/EEA, UK, Brazil LGPD, etc.), integrating a Consent Management Platform (CMP), or modifying the default consent posture.