verilog skills

Eriemon/verilog-generator

Skill Codex

Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed…

phamcuong21478/rtl-skills

Skill Claude Code

Generate a design proposal, documentation, and RTL backbone from a requirement file.