Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add phamcuong21478/rtl-skills --skill vdesigngit clone --depth 1 https://github.com/phamcuong21478/rtl-skillsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/phamcuong21478/rtl-skills/vdesign)<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vdesign"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vdesign/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vdesign"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vdesign.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00017 | $0.04777 |
| Opus 5 | $0.00009 | $0.02388 |
| Sonnet 5 | $0.00003 | $0.00955 |
| Haiku 4.5 | $0.00002 | $0.00478 |
Grade A, and why
vdesign scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 12d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 345 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Verilog Designer
Overview
This guide defines the workflow for generating a design proposal, documentation, and a skeleton RTL module from a Markdown requirement file.
The input is a .md requirement file that describes what the module should do, typically ./ddoc/<module>_req.md produced by varch. The output is:
- A proposal file with function description, architecture and algorithm if applicable
- A design documentation file
- A backbone Verilog file with
//@direction comments, ready for implementation byvfill
vdesign runs once per new submodule. Reused lib modules have no _req.md (they are already designed and documented), so there is nothing here to drive — vdesign simply skips them; varch still instantiates them in the skeleton.
Module Name Derivation
All output file names are derived from the module name, not the raw requirement file name. The module name is the requirement file base name with any trailing _req removed.
Example:
- requirement
./ddoc/foo_ctrl_req.md→ module namefoo_ctrl
Use this module name consistently for the proposal, documentation, and RTL backbone file names below.
Preconditions
Two stop conditions, checked before anything is written:
- Requirement file missing.
./ddoc/<module>_req.mddoes not exist → stop and report: runvarchfirst (or place a hand-written requirement file). Never design from a module name alone. - Target is the IP top. The module name resolves to
<ip>_top→ refuse. The top-level integration skeleton is owned byvarch(it has no_req.md, and its//@are integration notes, not fill directions);vdesigngenerates submodule backbones only.
Before You Start — Re-run Safety
vdesign overwrites three artifacts. Two of them carry hand-owned downstream content once the flow has progressed past vfill:
rtl/<module>.v— aftervfill, this holds the real implementation and every//@marker has been converted away. A blind re-generate destroys the implementation.ddoc/<module>_proposal.md—vfillrecords design updates and debug notes in its## Implementation Notes (vfill)section (seeded empty in Step 2). A blind re-generate clobbers them.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 12d ago First seen · 345 lines · 17 tokens per session scan A f1bcf2003bbb
vdesign is a skill published in the GitHub repository phamcuong21478/rtl-skills (13 stars, last pushed 3mo ago), licensed Apache-2.0. It adds 17 tokens to every session and 4,777 once invoked, about $0.0001 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
simulation
Use when materializing and running a module's UVM TB from an approved verification plan (regression, coverage); not for plan authoring or RTL changes.
simulation-plan
Use when generating or evolving the verification plan, scaffold specification, testpoints, and power scenarios for a module; not for materializing UVM TB or running EDA tools.
synthesis
Use when running Design Compiler synthesis, analyzing timing/area/power reports, supplementing SDC exceptions, or re-synthesizing after RTL changes; not for power analysis or static timing.
design-flow
Use when progressing IC design through stages, checking module status, or routing rework decisions; not for single-stage execution or artifact authoring.
lint-cdc
Use when running SpyGlass lint or CDC checks, analyzing violations, adding waivers, supplementing SGDC annotations, or re-running after RTL changes; not for synthesis or simulation.
power-analysis
Use when running gate-level power simulation + PT-PX averaged power analysis (SAIF flow) for PPA gating; not for RTL functional simulation, static timing, or time-resolved waveforms.