Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add chipweaver/veripower --skill design-flowgit clone --depth 1 https://github.com/chipweaver/veripowerWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/chipweaver/veripower/design-flow)<a href="https://agentmods.dev/skills/chipweaver/veripower/design-flow"><img src="https://agentmods.dev/badge/skills/chipweaver/veripower/design-flow/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/chipweaver/veripower/design-flow"><img src="https://agentmods.dev/badge/skills/chipweaver/veripower/design-flow.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00031 | $0.00925 |
| Opus 5.5 | $0.00012 | $0.00370 |
| Sonnet 5.5 | $0.00006 | $0.00185 |
| Haiku 4.5 | $0.00003 | $0.00093 |
Grade A, and why
design-flow scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 13d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 87 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Design Flow
Coordinate module stages, rework and delivery through
python3 <skill>/../../framework/scripts/kernel.py, written kernel.py below.
<skill> is this skill's directory; {module} contains events.jsonl,
intent/brainstorm.md and the stage trees.
The kernel owns events and scheduling. Stage executors own their workdir artifacts and close through the stage CLI, whether running in this conversation or in a subagent. While orchestrating, use the kernel rather than editing events or stage results directly. Inspect source when needed to understand an operation.
Use kernel.py status --module {module} to check current status. Command arguments are available
through kernel.py <command> --help.
Run the work
Run the kernel loop:
loop:
a = kernel.py decide --module {module} [--wake <rule>:<run>] [--closing]
execute(a) # actions below; launching a background executor does not wait for it
if a.action == DONE: finish
For DISPATCH, invoke the returned dispatch_args through the kernel CLI. The response prepares
the workdir and identifies the executor; it does not start that executor.
execution |
Start the work |
|---|---|
main-thread |
Invoke the returned skill in this conversation, acting as that stage's executor. |
task |
Render the stage prompt with the module, rule, skill and workdir from dispatch; launch an independent background executor with that prompt through the host adapter. |
Skill names are bare stage names. The host adapter supplies native skill loading and delegation.
After launching a background executor, query decide again so other ready work can proceed.
Confirm executor exit through the host before waking or reaping its run; a result file or YIELD
does not establish exit. Once it exits, pass --wake <rule>:<run> to decide, including when it
left no result. Carry out the returned action:
REAP: runkernel.py reap --module {module} --rule <rule> --run <run>, then query again. Reap uses that run's result; an absent result is handled as an incomplete execution.YIELD: report the running work and wait for an executor completion before resuming.ESCALATE: address the reported blocker under the authorization below, then querydecideagain. Wait when needed information or a reserved human decision is unavailable.kernel.py diagnoserecords a later addition or correction to repair ownership;--supersedesidentifies the diagnosis being replaced.DONE: deliver the conclusions and complete any acceptance in scope, as described below.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 13d ago Changed · +2 lines 4b3356a56977
- 1mo ago Changed · -55 lines 841481e691ae
- 1mo ago Changed · -9 lines 0ccb3dd33f9c
- 1mo ago First seen · 149 lines · 31 tokens per session scan A c431c99e1ef2
design-flow is a skill published in the GitHub repository chipweaver/veripower (10 stars, last pushed 7d ago), licensed MIT. It adds 31 tokens to every session and 925 once invoked, about $0.0001 per session on Opus 5.5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
vdesign
Generate a design proposal, documentation, and RTL backbone from a requirement file.
varch
Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton.
vfill
Implement Verilog code from an approved design proposal, then lint and simulate.
vflow
Scan project state to determine phase completion, write flowstatus.md, and orchestrate the full RTL design flow from architecture to documentation.
vsynth
Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power.
vexplain
Generate documentation for any RTL module from Verilog source files.