chipweaver
01Plugin Claude Code
ChipWeaver plugin marketplace.
4 2d ago A
tokens not measured
original MIT
veripower
02Plugin Claude Code
AI-assisted IC design flow skills — specification, RTL, lint/CDC, simulation, synthesis, timing analysis, and signoff.
4 2d ago A
tokens not measured
original MIT
PreToolUse
03Hook Claude Code
Runs before the agent uses a tool for Bash tool calls, executing commit_selfcheck.py via python3. From chipweaver/veripower.
4 2d ago A
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original MIT
SessionStart
04Hook Claude Code
Runs when a session starts, executing ensure_precommit.sh via bash. From chipweaver/veripower.
4 2d ago A
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copy · 50% MIT
veripower
05Settings file Claude Code
Agent settings declaring 2 hook events (PreToolUse, SessionStart).
4 2d ago A
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copy · 86% MIT
Instructions file
Instructions for chipweaver/veripower, covering claude.md — veripower plugin, pipeline, module layout, kernel & skill dispatch and reference docs.
4 2d ago A 1,758 tokens
original MIT
PostToolUse
07Hook
Runs after a tool call finishes for Bash tool calls, executing loop_after_task_dispatch.py via python3. From chipweaver/veripower.
4 2d ago A
tokens not measured
original MIT
brainstorm
08Skill Claude CodeCodex
Use when brainstorming a new module's requirements and architecture to produce the brainstorm.md the pipeline starts from; not for design.md, RTL, constraints, or any in-pipeline stage.
4 2d ago A 39 tokens
original MIT
design-flow
09Skill Claude CodeCodex
Use when progressing IC design through stages, checking module status, or routing rework decisions; not for single-stage execution or artifact authoring.
4 2d ago A 31 tokens
original MIT
env-precheck
10Skill Claude CodeCodex
Use when checking whether this machine's Python, EDA tools and licenses can actually run VeriPower's stages; not for any pipeline stage, module state, or design work.
4 2d ago A 39 tokens
original MIT
lint-cdc
11Skill Claude CodeCodex
Use when running SpyGlass lint or CDC checks, analyzing violations, adding waivers, supplementing SGDC annotations, or re-running after RTL changes; not for synthesis or simulation.
4 2d ago A 40 tokens
original MIT
Skill Claude CodeCodex
Use when running gate-level power simulation + PT-PX averaged power analysis (SAIF flow) for PPA gating; not for RTL functional simulation, static timing, or time-resolved waveforms.
4 2d ago A 43 tokens
original MIT
rtl-design
13Skill Claude CodeCodex
Use when writing or modifying Verilog/SystemVerilog RTL, or recording each child's file layout and constraint annotations; not for verification, lint, or synthesis.
4 2d ago A 34 tokens
original MIT
Skill Claude CodeCodex
Use when generating or evolving the verification plan, scaffold specification, testpoints, and power scenarios for a module; not for materializing UVM TB or running EDA tools.
4 2d ago A 38 tokens
original MIT
Skill Claude CodeCodex
Use when a simulation run fails and root-cause analysis is needed before a rework decision; not for fixing code, modifying state, or running regression.
4 2d ago A 36 tokens
original MIT
simulation
16Skill Claude CodeCodex
Use when materializing and running a module's UVM TB from an approved verification plan (regression, coverage); not for plan authoring or RTL changes.
4 2d ago A 34 tokens
original MIT
Skill Claude CodeCodex
Use when writing or reviewing design specification (design.md), defining interfaces or constraints (SDC/SGDC), or updating from rework feedback; not for RTL implementation or verification.
4 2d ago A 39 tokens
original MIT
synthesis
18Skill Claude CodeCodex
Use when running Design Compiler synthesis, analyzing timing/area/power reports, supplementing SDC exceptions, or re-synthesizing after RTL changes; not for power analysis or static timing.
4 2d ago A 42 tokens
original MIT
Skill Claude CodeCodex
Use when running static timing analysis on synthesis netlist, analyzing setup/hold violations, reviewing timing reports, or re-analyzing after synthesis changes; not for synthesis or power analysis.
4 2d ago A 41 tokens
original MIT