Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add phamcuong21478/rtl-skills --skill varchgit clone --depth 1 https://github.com/phamcuong21478/rtl-skillsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/phamcuong21478/rtl-skills/varch)<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/varch"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/varch/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/varch"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/varch.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00030 | $0.03313 |
| Opus 5.5 | $0.00012 | $0.01325 |
| Sonnet 5.5 | $0.00006 | $0.00663 |
| Haiku 4.5 | $0.00003 | $0.00331 |
Grade A, and why
varch scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 1mo ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 239 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Verilog Architect
Overview
This guide defines the workflow for decomposing a top-level IP requirement into submodules, defining their interfaces, and capturing the result in an architecture document that drives the per-submodule requirement files (ready for vdesign) and the top-level skeleton.
The input is a top-level IP requirement .md file. The outputs are:
- An architecture document
./ddoc/<ip>_arch.md— the canonical structural source (decomposition, block diagram, interface table, parameter propagation map). This is the one file the user edits to change the architecture and re-run. - One requirement
.mdfile per submodule in./ddoc/, derived from the architecture document - A top-level integration skeleton in
./rtl/, derived from the architecture document
varch is idempotent and architecture-document-driven: on a re-run, ./ddoc/<ip>_arch.md is the source of truth and the requirement files and skeleton are regenerated from it (see Step 6). On the first run the document does not exist yet, so Steps 1–2 create it.
Re-run: if
./ddoc/<ip>_arch.mdalready exists, it is authoritative. Read it instead of re-deriving the decomposition from scratch, apply whatever the user changed in it (or asks for), then go to Step 6 (regenerate), which ends in the Step 5 self-check. Steps 1–4 below describe the first run that builds the document.
Step 1 - Analyze Requirements and Propose Decomposition
Read the top-level IP requirement .md file and extract the design intent.
Before proposing a new decomposition, check ./lib for any existing library modules that already cover part of the required functionality. Read each candidate's <module>.md documentation to understand its interface and behaviour — the docs follow the ModuleDocContract and are usable without reading the RTL, so there is no need to run vexplain. Only fall back to reading the source (or vexplain) if a lib module's doc is missing or does not state its ports/parameters. Reuse such modules rather than redesigning.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 1mo ago First seen · 239 lines · 30 tokens per session scan A 58c66328ab07
varch is a skill published in the GitHub repository phamcuong21478/rtl-skills (18 stars, last pushed 4mo ago), licensed Apache-2.0. It adds 30 tokens to every session and 3,313 once invoked, about $0.0001 per session on Opus 5.5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
power-analysis
Build and check power experiments, calculate averaged gate-level power with SAIF and PT-PX, and assess the results against the task's power requirements; not for functional regression or static timing analysis.
design-flow
Use when progressing IC design through stages, checking module status, or routing rework decisions; not for single-stage execution or artifact authoring.
simulation-plan
Use when generating or evolving a module's verification strategy, testpoints, TB scaffold and power measurement plan; not for implementing the testbench or running a regression.
simulation
Implement, review and run a module's functional testbench, diagnose verification failures and assess coverage; not for changing upstream RTL or requirements.
rtl-design
Use when writing or modifying RTL and its file/constraint annotations, reviewing implementation against requirements, or repairing an implementation defect; not for running synthesis or functional regression as a pipeline stage.
synthesis
Establish the synthesized implementation, its constraints and measurements, and assess them against the task's requirements.