Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add chipweaver/veripower --skill rtl-designgit clone --depth 1 https://github.com/chipweaver/veripowerWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/chipweaver/veripower/rtl-design)<a href="https://agentmods.dev/skills/chipweaver/veripower/rtl-design"><img src="https://agentmods.dev/badge/skills/chipweaver/veripower/rtl-design/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/chipweaver/veripower/rtl-design"><img src="https://agentmods.dev/badge/skills/chipweaver/veripower/rtl-design.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00039 | $0.00661 |
| Opus 5.5 | $0.00016 | $0.00264 |
| Sonnet 5.5 | $0.00008 | $0.00132 |
| Haiku 4.5 | $0.00004 | $0.00066 |
Grade A, and why
rtl-design scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 1mo ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 56 lines — stays where its author put it; the contents beside it link to each section on GitHub.
RTL Design
Implement the required behavior and boundary, and resolve findings before delivering the RTL.
Read {workdir}/dispatch.json for the input locations. design.md proposes an architecture;
requirements.json, the original intent, top-io.json and clocks.json establish the applicable
requirements and boundary. Read the sources needed to assess a discrepancy. Upstream artifacts
are read-only; write this stage's work under {workdir}.
Implement and review
Choose the module split to suit the task. Continue from carried RTL and use changed inputs,
reported failures and decisions in dispatch.json to scope repairs. Preserve unaffected work.
Implement directly or delegate cohesive parts using child-task-contract.md.
Coordinate shared interfaces and avoid concurrent edits to the same files.
Apply the toolchain constraints in coding-rules.md, whether implementing directly or delegating.
Deliver src/, rtl-files.json and constraint-annotations.json. Their formats are in the matching
reference schemas. Integrate sources into one global compilation order in rtl-files.json, with
the required include search paths. Keep implementation annotations grouped by their owner.
Compile the complete file set before closure.
Have an independent reviewer assess the delivered RTL using rtl-review-task-contract.md. Read the findings and their supporting evidence. Resolve disagreements against the requirement, implementation and measurements; request focused reassessment when evidence changes and retain the reviewer's findings.
Assess findings by their acceptance impact, including those labeled non-blocking. Repair demonstrated violations here or return them to their owner; identify evidence needed to assess unmeasured risks.
Use targeted checks to validate repairs and consider affected integration behavior. Changes to acceptance meaning require the user's actual authorization. An authorized change establishes a new scope; it does not prove a previously unsupported technical claim.
What ships with it
9 files beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
- references/child-task-contract.md 1.3 KB
- references/coding-rules.md 765 B
- references/constraint-annotations.schema.json 4.2 KB
- references/result.schema.json 1.7 KB
- references/rtl-files.schema.json 1.4 KB
- references/rtl-review-task-contract.md 1.9 KB
- scripts/rtl/__init__.py 0 B runs code
- scripts/rtl/__main__.py 1.7 KB runs code
- scripts/rtl/result.py 3.6 KB runs code
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 1mo ago Changed · -16 lines · +10 tokens per session fe65a5bcb0d0
- 1mo ago Changed · -5 tokens per session 956ab73d5d5b
- 1mo ago Changed · +2 lines fc9c60594fa5
- 1mo ago Changed · +1 lines 6b1ebc6e38a9
- 1mo ago First seen · 69 lines · 34 tokens per session scan A 62710fa2a17a
rtl-design is a skill published in the GitHub repository chipweaver/veripower (10 stars, last pushed 7d ago), licensed MIT. It adds 39 tokens to every session and 661 once invoked, about $0.0002 per session on Opus 5.5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
vfill
Implement Verilog code from an approved design proposal, then lint and simulate.
vdesign
Generate a design proposal, documentation, and RTL backbone from a requirement file.
varch
Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton.
vflow
Scan project state to determine phase completion, write flowstatus.md, and orchestrate the full RTL design flow from architecture to documentation.
vsynth
Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power.
vexplain
Generate documentation for any RTL module from Verilog source files.