Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx agentmods add skills/chipweaver/veripower/rtl-designnpx skills add chipweaver/veripower --skill rtl-designgit clone --depth 1 https://github.com/chipweaver/veripowerWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/chipweaver/veripower/rtl-design)<a href="https://agentmods.dev/skills/chipweaver/veripower/rtl-design"><img src="https://agentmods.dev/badge/skills/chipweaver/veripower/rtl-design.svg" alt="Measured on agentmods" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5 | $0.00034 | $0.01348 |
| Opus 5 | $0.00017 | $0.00674 |
| Sonnet 5 | $0.00007 | $0.00270 |
| Haiku 4.5 | $0.00003 | $0.00135 |
Grade A, and why
rtl-design scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 4d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 69 lines — stays where its author put it; the contents beside it link to each section on GitHub.
RTL Design
Your sole responsibility: turn manifest.json's child roster into authored RTL. You are a thin dispatcher — the per-child sub-Tasks author every .v file, and a reviewer per child reads it back against its intent. You hold no RTL body, and every fix lands through a child re-dispatch.
Iron Rule
design.mdand the per-child<child>.mdare the intent source. Never modify either; no RTL-level adjustment overrides an architectural decision.
Artifacts
<skill> is this skill's own base directory, named on the first line of this file.
Read {workdir}/dispatch.json for this round's inputs: its inputs table maps each upstream key to a location, so <key>/<subpath> is how you address one. Every key resolves to the specification stage root, so <design> reaches its sibling sidecars too.
caused_by and scope name what this round is about, and they are independent: scope is what drifted under you, caused_by is the failing runs waiting on you (read each envelope). A round can carry both; answer both. reasons is a human's judgment on this repair. It outranks your own reading of the files. If you disagree, say so in result.json instead of acting against it.
| Path | What it is |
|---|---|
<manifest>/manifest.json |
The child roster: module (= <top_module>) + children[] (name / doc / rtl_modules[]). Drives the fan-out |
<children>/ (the per-child designs) |
Per-child sub-design — frontmatter + §2 Interface + §3 Internal Behavior are what each child derives its RTL from |
<design>/top-io.json, interconnects.json, clocks.json |
The boundary, the cut edges, the clocks. Passed by path into the sub-Tasks |
<design>/ppa.json |
The area / timing-slack / power targets this RTL is judged against. Passed by path into the sub-Tasks |
Everything below is produced under {workdir}. Each JSON sidecar's shape is references/<name>.schema.json.
| Path | What it is |
|---|---|
src/ |
The authored RTL, the <top_module> file among it — delivered as one tree |
rtl-files.json |
Per-child files[] + incdirs[], keys in manifest order. Every downstream filelist is generated from it — no stage parses a text file list |
constraint-annotations.json |
Per-child SGDC/SDC annotations in real module names, read by lint-cdc and synthesis |
semantic-review/ |
The intent reviews, written by their reviewers. Prose, not a verdict — delivered as one tree, so what you call the files in it is yours |
result.json |
The status envelope, written only by finalize |
What ships with it
11 files beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
- references/child-task-contract.md 5.4 KB
- references/coding-rules.md 10 KB
- references/constraint-annotations.schema.json 4.6 KB
- references/result.schema.json 1.9 KB
- references/rtl-files.schema.json 3.3 KB
- references/rtl-review-task-contract.md 3.6 KB
- scripts/rtl/__init__.py 0 B runs code
- scripts/rtl/__main__.py 2.3 KB runs code
- scripts/rtl/_ledger.py 3.2 KB runs code
- scripts/rtl/partition.py 3.0 KB runs code
- scripts/rtl/result.py 4.8 KB runs code
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 4d ago First seen · 69 lines · 34 tokens per session scan A 62710fa2a17a
rtl-design is a skill published in the GitHub repository chipweaver/veripower (4 stars, last pushed 4d ago), licensed MIT. It adds 34 tokens to every session and 1,348 once invoked, about $0.0002 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
vdesign
Generate a design proposal, documentation, and RTL backbone from a requirement file.
varch
Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton.
vfill
Implement Verilog code from an approved design proposal, then lint and simulate.
vflow
Scan project state to determine phase completion, write flowstatus.md, and orchestrate the full RTL design flow from architecture to documentation.
vsynth
Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power.
vexplain
Generate documentation for any RTL module from Verilog source files.