Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add phamcuong21478/rtl-skills --skill vexplaingit clone --depth 1 https://github.com/phamcuong21478/rtl-skillsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/phamcuong21478/rtl-skills/vexplain)<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vexplain"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vexplain/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vexplain"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vexplain.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00015 | $0.01867 |
| Opus 5 | $0.00008 | $0.00933 |
| Sonnet 5 | $0.00003 | $0.00373 |
| Haiku 4.5 | $0.00002 | $0.00187 |
Grade A, and why
vexplain scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 12d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 116 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Verilog Reader
Overview
This guide defines the workflow for generating documentation for a Verilog RTL
module from its source files. The RTL is the ground truth: the generated document
describes the module as implemented, accurately enough that another skill can
instantiate, drive, and reason about it without reading the source (see
.claude/skills/shared/ModuleDocContract.md).
Target Resolution & Name Derivation
The input is a single target module, identified by a file path or a module name. Resolve it to one top-level Verilog source file:
- A path under
./rtlor./libis the target directly. - A bare module name resolves to
./rtl/<module>.v, or to a./libmodule — either./lib/<module>.v(single-file) or./lib/<module>/<module>.v(multi-file, where the top file shares the module's name).
The module name is the source file's base name. All output names derive from
it, not from any partial path. Other .v files inside a multi-file ./lib/<mod>/
folder are submodules, not separate targets (see analysis order below).
If a single .v file declares more than one module, the target is the module
whose name matches the file base name; the others are treated as submodules.
Before You Start — Re-run Safety
vexplain overwrites the module document. Two cases need care:
- Existing doc — confirm first. An
rtl/doc/<module>.mdmay be a pre-implementationvdesigndraft, and alib/<module>.mdis the canonical reference for a reusable module. Generating a missing doc is the intended use; overwriting an existing one is destructive — confirm with the user first, then regenerate wholesale from the RTL (now ground truth). - Unfilled backbone — stop. If the target RTL still contains
//@markers (vflow's incompleteness marker,CodingStyle §18), it is avdesignbackbone thatvfillhas not implemented. Stop and report; do not document empty logic. Pre-implementation intent isvdesign's job.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 12d ago First seen · 116 lines · 15 tokens per session scan A df641650774b
vexplain is a skill published in the GitHub repository phamcuong21478/rtl-skills (11 stars, last pushed 3mo ago), licensed Apache-2.0. It adds 15 tokens to every session and 1,867 once invoked, about $0.0001 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
simulation
Use when materializing and running a module's UVM TB from an approved verification plan (regression, coverage); not for plan authoring or RTL changes.
simulation-plan
Use when generating or evolving the verification plan, scaffold specification, testpoints, and power scenarios for a module; not for materializing UVM TB or running EDA tools.
synthesis
Use when running Design Compiler synthesis, analyzing timing/area/power reports, supplementing SDC exceptions, or re-synthesizing after RTL changes; not for power analysis or static timing.
design-flow
Use when progressing IC design through stages, checking module status, or routing rework decisions; not for single-stage execution or artifact authoring.
lint-cdc
Use when running SpyGlass lint or CDC checks, analyzing violations, adding waivers, supplementing SGDC annotations, or re-running after RTL changes; not for synthesis or simulation.
power-analysis
Use when running gate-level power simulation + PT-PX averaged power analysis (SAIF flow) for PPA gating; not for RTL functional simulation, static timing, or time-resolved waveforms.