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systemverilog skills

13 tagged systemverilog, measured the same way as everything else here.

Browse within: chip-design 22rtl-design 22claude-code-plugin 12rtl 10verilog 10

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vdesign

01

phamcuong21478/rtl-skills

Skill Claude Code

Generate a design proposal, documentation, and RTL backbone from a requirement file.

not rated 16 4mo ago A 17 tokens original Apache-2.0

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