systemverilog skills

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Generate a design proposal, documentation, and RTL backbone from a requirement file.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Implement Verilog code from an approved design proposal, then lint and simulate.

chipweaver/veripower

Skill Claude CodeCodex

Use when a simulation run fails and root-cause analysis is needed before a rework decision; not for fixing code, modifying state, or running regression.

chipweaver/veripower

Skill Claude CodeCodex

Use when materializing and running a module's UVM TB from an approved verification plan (regression, coverage); not for plan authoring or RTL changes.

chipweaver/veripower

Skill Claude CodeCodex

Use when running Design Compiler synthesis, analyzing timing/area/power reports, supplementing SDC exceptions, or re-synthesizing after RTL changes; not for power analysis or static timing.