Claude Code skills & agents that automate a full RTL/Verilog design flow - architecture, RTL coding, lint, simulation, self-checking testbenches, regression, debug, Vivado synthesis, and docs - driven from a one-page IP spec.
This repository also configures its own agents. See what rtl-skills tells them →
Skill Claude Code
Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton.
Skill Claude Code
Trace failing signals through the RTL hierarchy, classify root cause, and write a debug report per issue — no fix is proposed.
Skill Claude Code
Generate a design proposal, documentation, and RTL backbone from a requirement file.
Skill Claude CodeCodex
Aggregate all per-module documentation into a single comprehensive IP document.
Skill Claude Code
Generate documentation for any RTL module from Verilog source files.
Skill Claude Code
Implement Verilog code from an approved design proposal, then lint and simulate.
Skill Claude CodeCodex
Scan project state to determine phase completion, write flowstatus.md, and orchestrate the full RTL design flow from architecture to documentation.
Skill Claude Code needs its repo
Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power.
Skill Claude CodeCodex
Scaffold a Makefile-driven, CPU-bus-controlled testbench project for an IP and generate a comprehensive set of self-checking testcases, validate each with make, and write a testcase list.
Skill Claude Code needs its repo
Run all IP-level testcases from tclist.md through the bench Makefile, capture results, and write per-failure issue reports with no fix suggestions.
At most 3 mods per repository are shown here, and a mod shipped inside a plugin is left to that plugin's page — the rest are on their repository pages: