Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add phamcuong21478/rtl-skills --skill vdebuggit clone --depth 1 https://github.com/phamcuong21478/rtl-skillsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/phamcuong21478/rtl-skills/vdebug)<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vdebug"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vdebug/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vdebug"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vdebug.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00027 | $0.04241 |
| Opus 5.5 | $0.00011 | $0.01696 |
| Sonnet 5.5 | $0.00005 | $0.00848 |
| Haiku 4.5 | $0.00003 | $0.00424 |
Grade C, and why
vdebug scanned grade C with 1 finding against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 1mo ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Recursive force deletehighDestructive command
rm -rf with a variable or a broad path is one typo away from removing the wrong tree.
rm -rf sim/tb_<name> How it starts
The opening of the file, as written. The whole thing — 335 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Verilog Debugger
Overview
This guide defines the workflow for diagnosing RTL failures captured in issue reports. Starting from the failure context, the skill traces signal paths statically through the module hierarchy, observes intermediate nodes with a temporary testbench probe when needed, and classifies the root cause with file-level precision.
This skill diagnoses root cause only. It does not propose or apply any code change.
Operating Modes
| Mode | Input | Use case |
|---|---|---|
| Single | IP name + issue number (e.g. foo issue_003) |
Deep-dive on one specific issue |
| Batch | IP name only (e.g. foo) |
Process all open issues; group by root cause |
In batch mode, cluster before tracing to avoid re-tracing a shared root once per failure:
- Triage every issue file first (cheap — just the
[ERROR]register address each maps to) and group issues whose failing output is the same or adjacent. - Read the IP-level context (
doc/<ip_name>.md,rtl/<ip_name>_top.v) once and reuse it for all clusters. - Trace each cluster's shared signal path once (Step 3), then write a report for every issue in the cluster from that single trace.
Process clusters from the lowest issue number upward.
Outputs
./issue/<ip_name>/debug_NNN_<tcname>.md— one per issue analyzed (NNN matches the issue number)./issue/<ip_name>/debug_summary.md— batch mode only; root cause grouping across all analyzed issues
Before You Start — Re-run Safety & Scope
vdebug is a read-and-diagnose skill with one deliberate, temporary write: the
optional probe in Step 4. Two scope rules make re-runs safe:
- Never write to
rtl/orlib/. Diagnosis reads synthesizable source but never edits it. All probing happens in a disposable testbench include (tb/<ip_name>/vdebug_probe.svh, Step 4) that reaches internal nodes by hierarchical reference (u_dut.<inst>.<sig>) — the DUT is never instrumented. - Clean stale probes first. A prior run may have aborted between Step 4A and
4C. Before starting, confirm no probe artifact survives:
grep -rn "vdebug probe" tb/<ip_name>/returns nothing,tb/<ip_name>/vdebug_probe.svhdoes not exist, and notb_*.svstill`includes it. Remove any leftover before diagnosing.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 1mo ago First seen · 335 lines · 27 tokens per session scan C 49c30c2a67d3
vdebug is a skill published in the GitHub repository phamcuong21478/rtl-skills (18 stars, last pushed 4mo ago), licensed Apache-2.0. It adds 27 tokens to every session and 4,241 once invoked, about $0.0001 per session on Opus 5.5. A static security scan graded it C with 1 finding (recursive force delete). No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
lint-cdc
Check RTL lint and clock-domain crossings with SpyGlass, evaluate violations and justified waivers, and close the current assessment.
power-analysis
Build and check power experiments, calculate averaged gate-level power with SAIF and PT-PX, and assess the results against the task's power requirements; not for functional regression or static timing analysis.
design-flow
Use when progressing IC design through stages, checking module status, or routing rework decisions; not for single-stage execution or artifact authoring.
simulation-plan
Use when generating or evolving a module's verification strategy, testpoints, TB scaffold and power measurement plan; not for implementing the testbench or running a regression.
simulation
Implement, review and run a module's functional testbench, diagnose verification failures and assess coverage; not for changing upstream RTL or requirements.
rtl-design
Use when writing or modifying RTL and its file/constraint annotations, reviewing implementation against requirements, or repairing an implementation defect; not for running synthesis or functional regression as a pipeline stage.