Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add phamcuong21478/rtl-skills --skill vdocgit clone --depth 1 https://github.com/phamcuong21478/rtl-skillsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/phamcuong21478/rtl-skills/vdoc)<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vdoc"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vdoc/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vdoc"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vdoc.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00014 | $0.01128 |
| Opus 5 | $0.00007 | $0.00564 |
| Sonnet 5 | $0.00003 | $0.00226 |
| Haiku 4.5 | $0.00001 | $0.00113 |
Grade A, and why
vdoc scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 12d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 109 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Verilog IP Documenter
Overview
This guide defines the workflow for collecting all documentation generated during the development process and synthesizing it into a single, comprehensive IP-level document.
The input is the IP name. The output is a single Markdown file ./doc/<ip_name>.md covering the full IP.
Step 1 - Collect Documentation Sources
Read the module docs as the primary source — do not also read every _req.md
and _proposal.md. The ModuleDocContract guarantees ./doc/<module>.md is
complete enough to "instantiate, drive, and reason about the module without
reading its RTL," so it already carries the interface and functional content this
skill aggregates. Reading the requirement and proposal for every module on top of
the doc is redundant and the largest token cost here; pull from them only as a
fallback (see the Read priority below).
| Source | Location | Content | When to read |
|---|---|---|---|
| Module docs | ./doc/<module>.md |
Per-module interface and functional description | Always — primary source |
| Top-level skeleton | ./rtl/<ip_name>_top.v |
Top-level ports and inter-module wiring | Always |
| Library module docs | ./lib/**/<module>.md |
Reused library module documentation | Always (for reused modules) |
| Synthesis report | ./synth/<ip_name>/synth_report.md |
Utilization, Fmax, power | If present (grep the summary tables, §7) |
| Proposals | ./ddoc/<module>_proposal.md |
Architecture, algorithm, timing diagrams | Fallback only — when the module doc lacks the algorithm/timing detail the Architecture section (§2) needs |
| Requirements | ./ddoc/<module>_req.md |
Original per-module requirements | Rarely — only to resolve a contradiction in a module doc |
Build a list of all submodules in the IP by walking the instantiation hierarchy from the top-level skeleton, following the shared procedure in .claude/skills/shared/HierarchyFilelist.md (use its grep-based extraction — do not read every RTL file).
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 12d ago First seen · 109 lines · 14 tokens per session scan A c22b505dbef1
vdoc is a skill published in the GitHub repository phamcuong21478/rtl-skills (13 stars, last pushed 3mo ago), licensed Apache-2.0. It adds 14 tokens to every session and 1,128 once invoked, about $0.0001 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
simulation
Use when materializing and running a module's UVM TB from an approved verification plan (regression, coverage); not for plan authoring or RTL changes.
simulation-plan
Use when generating or evolving the verification plan, scaffold specification, testpoints, and power scenarios for a module; not for materializing UVM TB or running EDA tools.
synthesis
Use when running Design Compiler synthesis, analyzing timing/area/power reports, supplementing SDC exceptions, or re-synthesizing after RTL changes; not for power analysis or static timing.
design-flow
Use when progressing IC design through stages, checking module status, or routing rework decisions; not for single-stage execution or artifact authoring.
lint-cdc
Use when running SpyGlass lint or CDC checks, analyzing violations, adding waivers, supplementing SGDC annotations, or re-running after RTL changes; not for synthesis or simulation.
power-analysis
Use when running gate-level power simulation + PT-PX averaged power analysis (SAIF flow) for PPA gating; not for RTL functional simulation, static timing, or time-resolved waveforms.