Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add chipweaver/veripower --skill synthesisgit clone --depth 1 https://github.com/chipweaver/veripowerWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/chipweaver/veripower/synthesis)<a href="https://agentmods.dev/skills/chipweaver/veripower/synthesis"><img src="https://agentmods.dev/badge/skills/chipweaver/veripower/synthesis/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/chipweaver/veripower/synthesis"><img src="https://agentmods.dev/badge/skills/chipweaver/veripower/synthesis.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00023 | $0.00869 |
| Opus 5.5 | $0.00009 | $0.00348 |
| Sonnet 5.5 | $0.00005 | $0.00174 |
| Haiku 4.5 | $0.00002 | $0.00087 |
Grade A, and why
synthesis scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 1mo ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 74 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Synthesis
Establish the implementation and evidence needed for the current task. Read dispatch.json,
the original intent, requirements, RTL and constraints, and the materials carried into {workdir}. A new dispatch
requires a current conclusion; it does not prescribe a new synthesis. Use measurements whose
implementation, conditions and scope still apply, and perform the work the remaining questions need.
Write under {workdir}; upstream inputs remain read-only. The framework carries previously
published setup and products into this directory, without the old verdict. Keep useful analysis
and comparison material in evidence/.
Tools
<skill> is this skill's directory. Setup, execution and judgment are independent operations:
python3 <skill>/scripts/synthesis/__main__.py bootstrap --workdir {workdir}
Bootstrap refreshes scripts/rtl_load.tcl and constraints.sdc from upstream inputs. It installs
missing config.tcl, constraints.local.sdc and driver scripts, preserving existing copies of these
editable files. manifest.module supplies the top; rtl-files.json supplies source order and include
paths. Adapt scripts/dc_run.tcl for the required calculation. The supplied script maps
RTL using DC-Ultra; examining an existing mapped implementation may require different tool work.
Render the design's declared generated clocks and timing exceptions from
constraint-annotations.json into constraints.local.sdc, which follows constraints.sdc.
Check names and divider ratios against RTL. Record the engineering basis for exceptions, local
clock uncertainty and library-specific IO settings alongside the SDC commands.
Set the actual LIB_DB and WIRE_LOAD_MODEL (a library model or none) in config.tcl, then run:
cd {workdir}
python3 <skill>/scripts/synthesis/__main__.py run --workdir .
run computes in a temporary directory using the current setup. Scripts write outputs relative
to out/ and reports/ in their working directory, including supplementary reports, and read
inputs at explicit paths. Existing reports are withdrawn;
out/ and reports/ are replaced only after successful, readable output. The log and failed
calculation remain available until retry. Wait for completion and inspect warnings and conditions.
What ships with it
8 files beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
- references/result.schema.json 2.5 KB
- scripts/synthesis/__init__.py 0 B runs code
- scripts/synthesis/__main__.py 3.3 KB runs code
- scripts/synthesis/bootstrap.py 6.6 KB runs code
- scripts/synthesis/execute.py 2.0 KB runs code
- scripts/synthesis/requirements.py 2.9 KB runs code
- scripts/synthesis/result.py 10.0 KB runs code
- templates/scripts/dc_run.tcl 4.7 KB
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 1mo ago Changed · -108 lines · -19 tokens per session edd5ba46c032
- 1mo ago Changed · -1 lines 8476e2c6b646
- 1mo ago Changed · +14 lines 9e8a49ecb4c4
- 1mo ago First seen · 169 lines · 42 tokens per session scan A ef941c3ecd8b
synthesis is a skill published in the GitHub repository chipweaver/veripower (10 stars, last pushed 7d ago), licensed MIT. It adds 23 tokens to every session and 869 once invoked, about $0.0001 per session on Opus 5.5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
vdesign
Generate a design proposal, documentation, and RTL backbone from a requirement file.
varch
Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton.
vfill
Implement Verilog code from an approved design proposal, then lint and simulate.
vflow
Scan project state to determine phase completion, write flowstatus.md, and orchestrate the full RTL design flow from architecture to documentation.
vsynth
Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power.
vexplain
Generate documentation for any RTL module from Verilog source files.