Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx agentmods add skills/chipweaver/veripower/synthesisnpx skills add chipweaver/veripower --skill synthesisgit clone --depth 1 https://github.com/chipweaver/veripowerWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/chipweaver/veripower/synthesis)<a href="https://agentmods.dev/skills/chipweaver/veripower/synthesis"><img src="https://agentmods.dev/badge/skills/chipweaver/veripower/synthesis.svg" alt="Measured on agentmods" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5 | $0.00042 | $0.02506 |
| Opus 5 | $0.00021 | $0.01253 |
| Sonnet 5 | $0.00008 | $0.00501 |
| Haiku 4.5 | $0.00004 | $0.00251 |
Grade A, and why
synthesis scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 4d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 169 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Synthesis
Your sole responsibility: carry this module's declared timing exceptions into the SDC, converge
Design Compiler against it, and close the run through the synthesis CLI.
Iron Rule
- Write only under
{workdir}. Every injected input location is read-only, as is every other stage's output. - Scripts are black boxes, never Read their source. Invoke them per this skill's documented
command lines (flags via
--help); on a non-zero exit act on the documented failure protocol (stderr, stdout verdict), not the source. Sole exception: debugging a suspected bug in a script itself.
What you read, and what you edit
<skill> is this skill's own base directory, named on the first line of this file.
{workdir}/dispatch.json carries the inputs table below, so <key> denotes a location and you
read <key>/<subpath>. It also carries scope and caused_by when the kernel knows what changed
since your last run: those narrow which inherited exceptions you re-check and which violations you
triage, never which declarations you render — step 2 carries all of them every round, because the
SDC dc_shell reads is rebuilt every round.
| Path | Use |
|---|---|
<annotations>/constraint-annotations.json |
The sdc block per child: every timing exception and generated clock this RTL implies, in real module names. Its authors declared it and this stage is its only consumer. Schema: skills/rtl-design/references/constraint-annotations.schema.json. |
<rtl>/rtl-files.json |
Per-child file layout, which bootstrap turns into scripts/rtl_load.tcl. The RTL itself is under <rtl> too, and step 2 reads it for divider ratios. Schema: skills/rtl-design/references/rtl-files.schema.json. |
<sdc>/constraints/<TOP>.sdc |
Clocks and IO delays from specification. bootstrap reads it every round, so a correction here arrives on its own; it is not yours to restate or override. |
<ppa>/ppa.json |
The area and slack targets this run is judged against. finalize reads them itself; you read them when deciding which side of a PPA miss is wrong. Schema: skills/specification/references/ppa.schema.json. |
What ships with it
9 files beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
- references/result.schema.json 2.9 KB
- scripts/synthesis/__init__.py 0 B runs code
- scripts/synthesis/__main__.py 3.7 KB runs code
- scripts/synthesis/bootstrap.py 12 KB runs code
- scripts/synthesis/result.py 12 KB runs code
- templates/env.sh 824 B runs code
- templates/Makefile 1.3 KB
- templates/README.md 1.2 KB
- templates/scripts/dc_run.tcl 4.3 KB
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 4d ago First seen · 169 lines · 42 tokens per session scan A ef941c3ecd8b
synthesis is a skill published in the GitHub repository chipweaver/veripower (4 stars, last pushed 5d ago), licensed MIT. It adds 42 tokens to every session and 2,506 once invoked, about $0.0002 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
vdesign
Generate a design proposal, documentation, and RTL backbone from a requirement file.
varch
Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton.
vfill
Implement Verilog code from an approved design proposal, then lint and simulate.
vflow
Scan project state to determine phase completion, write flowstatus.md, and orchestrate the full RTL design flow from architecture to documentation.
vsynth
Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power.
vexplain
Generate documentation for any RTL module from Verilog source files.