Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add phamcuong21478/rtl-skills --skill vfillgit clone --depth 1 https://github.com/phamcuong21478/rtl-skillsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/phamcuong21478/rtl-skills/vfill)<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vfill"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vfill/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vfill"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vfill.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00017 | $0.02680 |
| Opus 5 | $0.00009 | $0.01340 |
| Sonnet 5 | $0.00003 | $0.00536 |
| Haiku 4.5 | $0.00002 | $0.00268 |
Grade A, and why
vfill scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 11d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 222 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Verilog Writer
Overview
This guide defines the workflow for implementing a Verilog module from an approved design proposal.
Before starting, read:
- The target Verilog source file — for
//@annotations and port declarations - The proposal file
./ddoc/<module_name>_proposal.md(same folder as the requirement file) — this is the source of truth for the implementation
Prerequisites
| Tool | Purpose | Check |
|---|---|---|
| Verilator | Verilog lint | verilator --version |
| xvlog | Xilinx Verilog compiler / lint | xvlog --version |
| xelab | Xilinx elaborator | xelab --version |
| xsim | Xilinx simulator | xsim --version |
Before running any lint or simulation step, verify the tool it needs is
installed using the check command above. If a required tool is missing, stop
and report which tool is unavailable — never fabricate lint, simulation, or
elaboration results. The Verilog can still be filled in (Step 1) without the
tools, but Steps 2 and 3 must not be reported as passed unless they actually
ran. (When invoked under vflow, this surfaces as ✗ BLOCKED (tool unavailable: <tool>) for the dependent phase.)
Before You Start — Re-run Safety
Before editing, check rtl/<module>.v for //@ markers (the signal vflow
uses for completion, CodingStyle §18):
| State | Detect | Action |
|---|---|---|
| Backbone | //@ markers present |
First run — implement, then convert every //@ away. |
| Already filled | no //@ left / real logic present |
Filled before: do not re-fill from scratch. Make the requested change as an incremental edit, update the proposal's ## Implementation Notes (vfill) section in place rather than appending a duplicate, then re-lint and re-simulate. |
Step 1 - Fill in the Verilog Code
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 11d ago First seen · 222 lines · 17 tokens per session scan A 4024397ef63e
vfill is a skill published in the GitHub repository phamcuong21478/rtl-skills (11 stars, last pushed 3mo ago), licensed Apache-2.0. It adds 17 tokens to every session and 2,680 once invoked, about $0.0001 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
rtl-design
Use when writing or modifying Verilog/SystemVerilog RTL, or recording each child's file layout and constraint annotations; not for verification, lint, or synthesis.
simulation
Use when materializing and running a module's UVM TB from an approved verification plan (regression, coverage); not for plan authoring or RTL changes.
simulation-plan
Use when generating or evolving the verification plan, scaffold specification, testpoints, and power scenarios for a module; not for materializing UVM TB or running EDA tools.
synthesis
Use when running Design Compiler synthesis, analyzing timing/area/power reports, supplementing SDC exceptions, or re-synthesizing after RTL changes; not for power analysis or static timing.
design-flow
Use when progressing IC design through stages, checking module status, or routing rework decisions; not for single-stage execution or artifact authoring.
lint-cdc
Use when running SpyGlass lint or CDC checks, analyzing violations, adding waivers, supplementing SGDC annotations, or re-running after RTL changes; not for synthesis or simulation.