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Neosyn-Logic/cg-agent-kit

MCP server for FPGA hardware design in C⏚ - agents write a C-like HDL; the server compiles, checks, generates Verilog and synth-checks against the real toolchain.

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cg-agent-kit

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Neosyn-Logic/cg-agent-kit

MCP server Claude CodeCodexCursor

MCP server for FPGA hardware design in C⏚ — drive the open-source C⏚ Verilog compiler from an AI agent. Runs locally from the cg-agent-kit Python package. Needs 1 environment variable to run.

not rated 1 16d ago A tokens not measured original MIT