Streamline FPGA development with 8 Vivado/Vitis skills for HLS, RTL, synthesis, constraints, timing, and debug workflows
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Vitis HLS synthesis assistant for C/C++ to RTL conversion. Covers kernel development, pragma optimization, interface configuration, and synthesis report analysis. For post-synthesis implementation use vivado-impl, for timing analysis use vivado-analysis, for hardware debug use vivado-debug.
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help with Vivado design analysis, timing report interpretation, or timing closure. This includes reporttiming interpretation (slack calculation, path analysis, clock skew/uncertainty), reporttimingsummary signoff verification, reportqorassessment (QoR scoring 1-5, assessment…
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help writing XDC/SDC timing or physical constraints for Vivado FPGA designs. This includes clock definitions (createclock, creategeneratedclock, virtual clocks), I/O delay constraints (setinputdelay, setoutputdelay, DDR timing), timing exceptions (setfalsepath, setmulticyclepath…
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help with Vivado in-system debugging, hardware programming, or debug core configuration. This includes ILA (Integrated Logic Analyzer) configuration and trigger strategies, VIO (Virtual I/O) usage for signal monitoring and control, JTAG-to-AXI Master for AXI transaction generation…
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help with Vivado implementation strategy selection and optimization. This includes optdesign (logic optimization directives and options), placedesign (placement directives, congestion analysis, PSIP physical synthesis), physoptdesign (physical optimization …
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help with Vivado simulation strategy, flow selection, and debugging. This includes behavioral simulation (RTL functional verification), post-synthesis simulation (netlist functional verification), post-implementation timing simulation (SDF back-annotation, timing verification)…
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synthdesign option tuning, resource inference control (RAM/DSP/SRL/BRAM), hierarchy optimization (flattenhierarchy, KEEPHIERARCHY), OOC (out-of-context) synthesis, incremental synthesis, RTL linting…
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user wants to generate, write, or execute Vivado/Vitis TCL scripts for FPGA design flows. This includes creating projects, running synthesis/implementation, programming devices, working with IP Integrator block designs, debug core insertion, constraint management, simulation, and any Vivado…
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