amoslee2026/Babel

amoslee2026/Babel

Skill Claude Code

A design assistant that turns a rough idea into an architecture specification for a chip or hardware module. An architecture specification describes the major parts of a system and how they work together.

amoslee2026/Babel

Skill Claude Code

An automated checker for CDC and RDC violations in hardware designs. It uses an abstract syntax tree to compare clock domains and checks whether crossing signals are protected by two-flip-flop synchronizers.

amoslee2026/Babel

Skill Claude Code

A SystemVerilog source-code checker that runs Babel LSP or Verible linting tools. It requires synthesizable source code to have no syntax errors and allows verification-only constructs in testbenches.

amoslee2026/Babel

Skill Claude CodeCodex

Babel internal issue protocol — close a handoff after downstream agent picked it up or user signed off. Moves designs/ /.handoff/ .md to .handoff/closed/ (using mv per AGENTS.md), appends to handofflog.jsonl.

amoslee2026/Babel

Skill Claude Code

A code-review skill that examines RTL, or register-transfer-level hardware code, for quality, maintainability, timing risks, and other flaws. It uses an intentionally strict review style.

amoslee2026/Babel

Skill Claude Code

A coverage-reporting tool for Verilator simulations. It reads a coverage.dat file and simulation log, then reports functional and code coverage and checks whether coverage reached 100%.

amoslee2026/Babel

Skill Claude Code

A chip-design tool that creates a Magic layout floorplan script from design planning files and a compiled hardware netlist. A floorplan arranges major circuit blocks before detailed physical layout.

amoslee2026/Babel

Skill Claude CodeCodex

Babel internal issue protocol — create a labeled handoff between pipeline agents. Writes designs/ /.handoff/ .md and appends to handofflog.jsonl; best-effort gh issue create if gh available. Triggered by every guru/architect agent at handoff time.

amoslee2026/Babel

Skill Claude Code

A tool for creating Synopsys SDC timing-constraint files from clock, input/output timing, and path-exception settings. SDC is a text format used to describe timing requirements for digital hardware, and the output is checked with OpenSTA syntax validation.

amoslee2026/Babel

Skill Claude Code

A markdown plan generator for software and hardware verification. It expands a seed file into checkpoints, coverage goals, edge cases, random-test rules, and a test-case list.

amoslee2026/Babel

Skill Claude Code

A hardware-code analysis tool that scans RTL, or register-transfer-level hardware code, to find module dependencies and write a build file. It orders lower-level modules before the top-level module for tools such as Yosys and Verilator.

amoslee2026/Babel

Skill Claude Code

A shared quality gate for four hardware-development stages: RTL, synthesis, testing, and physical design. It runs parameterized acceptance checks through a common gate runner.

amoslee2026/Babel

Skill Claude Code

A tool that reads a specified CBB or protocol wiki file and turns its Interface or Ports section into tables of ports and parameters. CBB means a reusable building block in a hardware design.

amoslee2026/Babel

Skill Claude Code

A digital-circuit optimization tool that reads BLIF output from Yosys and runs a custom ABC script sequence. BLIF is a text format for describing logic circuits; ABC is a tool for optimizing them.

amoslee2026/Babel

Skill Claude Code

A tool runner for KLayout 0.30.8, a program for working with chip layout files. It exports GDSII files, runs layout design-rule checks, and verifies the exported result.

amoslee2026/Babel

Skill Claude Code

A chip physical-design tool wrapper that calls Magic for floorplanning, component placement, design-rule checks, and extracting circuit data from a layout. Design-rule checks look for physical layout violations.

amoslee2026/Babel

Skill Claude Code

A chip-design verification tool that compares a circuit's intended netlist with the connections extracted from its physical layout. LVS, or layout-versus-schematic, checks that the two representations match.

amoslee2026/Babel

Skill Claude Code

A tool runner for OpenSTA 2.5.0, which checks whether digital circuits meet their timing requirements. It performs static timing analysis during synthesis and after physical routing across process, voltage, and temperature conditions.

amoslee2026/Babel

Skill Claude Code

A chip-design tool that sends a placed circuit layout in DEF format to QRouter for detailed routing. Routing determines the physical connections between components on a chip.

amoslee2026/Babel

Skill Claude Code

A tool runner for Verilator 5.012, a simulator that compiles hardware RTL and testbenches and runs them. It produces simulation logs, coverage data, and VCD waveform files.

amoslee2026/Babel

Skill Claude Code

A hardware-design workflow that uses Yosys 0.35 to turn RTL—code describing digital circuits—into a gate-level netlist mapped to ASAP7 standard cells. It also produces a quality report and can run several synthesis jobs in parallel.

amoslee2026/Babel

Skill Claude CodeCodex

Babel internal issue protocol — list open handoffs by label. Scans designs//.handoff/.md (filtered by label) and best-effort merge with gh issue list. Used by all guru/architect agents at startup to pick up work.

amoslee2026/Babel

Skill Claude Code

A document generator for the internal design of chip modules, covering state machines, data paths, testing plans, and design-for-test work. A chip module is a hardware block that performs part of a larger chip’s job.

amoslee2026/Babel

Skill Claude Code

An abstract syntax tree parser for SystemVerilog RTL. An abstract syntax tree is a structured representation of source code; the resulting JSON can support clock-domain checks, signal-path tracing, and module-dependency analysis.