amoslee2026/Babel

AI-native Chiplet design flow based on open-source EDA toolchain

This repository also configures its own agents. See what Babel tells them →

52Stars on the repository
57Mods indexed here, across every type
8d agoLast push, which is what freshness is scored on
GPL-3.0Licence, which decides whether bodies are shown

bb-prd

25

amoslee2026/Babel

Skill Claude Code

A product requirements document generator for chips and reusable hardware blocks called IP. A PRD records what the product must do and the technical limits it must meet.

not rated 52 +1 changed 8d ago A 68 tokens GPL-3.0

bb-rtl-coder

26

amoslee2026/Babel

Skill Claude Code

A skill for writing synthesizable SystemVerilog RTL from microarchitecture documents. RTL is the hardware logic that can be turned into a circuit, and synthesizable code is suitable for that process.

not rated 52 +1 changed 8d ago A 70 tokens GPL-3.0

bb-search-cbb

27

amoslee2026/Babel

Skill Claude Code

A search tool for reusable Common Building Blocks, or CBBs, in a hardware wiki. It finds templates such as clock-gating and clock-synchronisation components and returns their paths.

not rated 52 +1 8d ago A 87 tokens GPL-3.0

bb-search-protocol

28

amoslee2026/Babel

Skill Claude Code

A search tool for protocol documentation in a hardware wiki, covering standards such as UART, AXI4-Lite, and UCIe. It returns matching document paths and summaries.

not rated 52 +1 8d ago A 72 tokens GPL-3.0

bb-spec-review

29

amoslee2026/Babel

Skill Claude Code

An adversarial reviewer for product and system specification documents. It checks PRDs, architecture specifications, and MAS documents for completeness, consistency, practical feasibility, and verification coverage.

not rated 52 +1 changed 8d ago A 84 tokens GPL-3.0

amoslee2026/Babel

Skill Claude Code

A hardware-signal analysis tool that follows a signal from its source to its destination across module levels and checks whether it crosses clock domains. A clock-domain crossing happens when a signal moves between parts of a chip running on different clocks.

not rated 52 +1 8d ago A 94 tokens GPL-3.0

amoslee2026/Babel

Skill Claude CodeCodex

A placeholder skill entry with no specific subject, capabilities, or workflow described.

not rated 52 +1 8d ago A 52 tokens GPL-3.0

amoslee2026/Babel

Skill Claude Code

A tool that extracts structured test points from verification plans into JSON and Markdown files. These test points can be used by tools that create hardware testbenches and test cases.

not rated 52 +1 8d ago A 80 tokens GPL-3.0

amoslee2026/Babel

Skill Claude Code

A tool that creates a SystemVerilog testbench harness for each hardware module from test points and RTL ports. A testbench is code that drives a hardware design and checks its results.

not rated 52 +1 8d ago A 86 tokens GPL-3.0

amoslee2026/Babel

Skill Claude Code

A tool that converts structured test points into executable SystemVerilog tasks, test registries, documentation, and run scripts. It creates targeted, boundary, reset, and CDC variations where the test-point category calls for them; CDC means clock-domain crossing.

not rated 52 +1 8d ago A 98 tokens GPL-3.0

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