spice-sim

Spice Simulation

Add a small ngspice-backed testbench to a .zen design.

Workflow

1. Confirm the target is simulation-capable by running a dummy sim. pcb sim <path/to/file.zen> --setup "* empty setup check"

2. If the SPICE model is missing, add it. Find a vendor model, download it, or create a simple behavioral model if needed. Wire it through the leaf component with spice_model=SpiceModel(...) before writing the testbench.

3. Create a focused testbench file. Use a generic package-local path such as <package>/testbench/test_<scenario>.zen.

4. Keep the structure simple:

• top docstring
• imports
• nets/interfaces
• module-under-test instantiation
• minimal external load or pull-ups
• one Simulation(...) block

1. Put sources and analysis inside Simulation.setup. Use raw ngspice for:

• DC
• PULSE(...)
• PWL(...)
• .control
• tran
• hardcopy

1. Write the plot to testbench/output/<scenario>.svg.

Simulation In Zener

Simulation is a Zener property loaded from @stdlib/properties.zen and attached as a normal top-level object:

load("@stdlib/properties.zen", "Simulation")

Simulation(
    name="SIM",
    setup="""
* raw ngspice goes here
.control
  tran 10u 10m
.endc
""",
)

The setup string is passed through as ngspice input. Put voltage sources, waveform definitions, analysis commands, and plot/export commands there.

Pattern

"""<Part> <scenario> simulation test."""

load("@stdlib/properties.zen", "Simulation")

Target = Module("../Target.zen")
Resistor = Module("@stdlib/generics/Resistor.zen")

VIN = Power(voltage="12V")
VOUT = Power()
GND = Ground()

Target(
    name="UUT",
    VIN=VIN,
    VOUT=VOUT,
    GND=GND,
)

Resistor(
    name="R_LOAD",
    value="10ohm",
    package="0603",
    P1=VOUT,
    P2=GND,
)

Simulation(
    name="SIM",
    setup="""
* <Part> <scenario>

V_IN VIN GND DC 12

.control
  tran 10u 10m

  set hcopydevtype = svg
  hardcopy output/<scenario>.svg v(VIN) v(VOUT) title "<Part> <scenario>" xlabel "Time" ylabel "Voltage"
.endc

""",
)