george11642/george-plugins — Skills

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7mo agoLast push, which is what freshness is scored on

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fpga

Skill Claude CodeCodex

Master FPGA skill covering Vivado, SystemVerilog/Verilog/VHDL, RTL design, timing closure, CDC, AXI interfaces, FSMs, pipelines, memory interfaces, HLS, verification, and hardware optimization. Uses Context7 MCP for up-to-date library docs. Use when FPGA, Verilog, VHDL, HDL, RTL, synthesis, or hardware design…

not rated 2 7mo ago A 82 tokens

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