Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add hdl-tools/analog-chip-design-agents --skill circuit-designgit clone --depth 1 https://github.com/hdl-tools/analog-chip-design-agentsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/hdl-tools/analog-chip-design-agents/circuit-design)<a href="https://agentmods.dev/skills/hdl-tools/analog-chip-design-agents/circuit-design"><img src="https://agentmods.dev/badge/skills/hdl-tools/analog-chip-design-agents/circuit-design/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/hdl-tools/analog-chip-design-agents/circuit-design"><img src="https://agentmods.dev/badge/skills/hdl-tools/analog-chip-design-agents/circuit-design.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00074 | $0.02787 |
| Opus 5 | $0.00037 | $0.01393 |
| Sonnet 5 | $0.00015 | $0.00557 |
| Haiku 4.5 | $0.00007 | $0.00279 |
Grade A, and why
circuit-design scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 11d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 262 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Skill: Circuit (Schematic) Design
Invocation
- If invoked by a user presenting a circuit design task: immediately spawn the
analog-chip-design-agents:circuit-design-orchestratoragent and pass the full user request and any available context. Do not execute stages directly. - If invoked by the
circuit-design-orchestratormid-flow (including fix-request servicing): do not spawn a new agent. Treat this file as read-only — return the requested stage rules, sign-off criteria, or loop-back guidance.
Spawning the orchestrator from within an active orchestrator run causes recursive delegation and must never happen.
Pre-run Context
Before executing or advising on any stage, read the following if they exist:
memory/circuit/knowledge.md— known topology pitfalls, successful sizing recipes, PDK device quirks. Incorporate its guidance into every stage decision.memory/circuit/run_state.md— current run identity (run_id,design_name,pdk,last_stage) for resume-after-interruption.
Purpose
Guide analog block design from topology choice through a sign-off-ready, ERC-clean schematic and SPICE netlist meeting the block's pre-layout electrical specs. Six stages with explicit QoR gates and loop-back criteria enforced by the circuit-design orchestrator.
Supported EDA Tools
Open-Source
- xschem (
xschem) — schematic capture and SPICE netlist export; de-facto open analog schematic tool, integrates with sky130/gf180mcu/ihp-sg13g2 PDKs (and the predictive academic PDKs freepdk45/asap7) - ngspice (
ngspice) — in-the-loop DC/AC sweeps during sizing - Qucs-S (
qucs-s) — schematic + simulation front-end - Hdl21 + VLSIR (
python -m hdl21) — programmatic (Python) analog schematic generation - BAG / BAG3 — generator-based analog design framework
- gm/Id toolkits — lookup-table-based sizing (Python; from characterized device data)
Proprietary (detect-only — never installed)
- Cadence Virtuoso Schematic Editor (
virtuoso) — schematic capture with ADE - Synopsys Custom Compiler (
custom_compiler) — schematic and design entry - Siemens Tanner S-Edit (
s-edit) — schematic capture - MunEDA WiCkeD / Siemens Solido — automated sizing, optimization, and yield
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 11d ago First seen · 262 lines · 74 tokens per session scan A fe57248693cf
circuit-design is a skill published in the GitHub repository hdl-tools/analog-chip-design-agents (22 stars, last pushed 3mo ago), licensed MIT. It adds 74 tokens to every session and 2,787 once invoked, about $0.0004 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
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