Skill Claude CodeCodex
Add a new RTL design as an RTL Scout benchmark — directory layout, the self-checking testbench contract, the addbenchmark.py generators, and porting an existing Verilog or Spire design. Use when integrating a new design (or an external benchmark suite) into the benchmarks/ folder.
Skill Claude CodeCodex
Delegate the optimization of ONE design-DB slot to the rtl-subcircuit subagent via the task tool. Dispatch only delegates — analyzing the result afterwards is a separate design-db-inspect step.
Skill Claude CodeCodex
Set up the verification oracle for an unverified (typically sequential) design-DB slot — author test stimulus, dry-run it with --check, then freeze it once with honest authorship. Required before any insert into such a slot.
Skill Claude CodeCodex
Advisory correctness check of a candidate design against a slot's verification oracle — PASS/FAIL, admits nothing, writes nothing. The iteration step before design-db-insert.
Skill Claude CodeCodex
Submit a candidate implementation to a design-DB slot through the verification gate. Spire-first — insert a .py design (source stored, correct by construction); Verilog also accepted. Seed the baseline floor first.
Skill Claude CodeCodex
Inspect and analyze design-DB slots — list slots, read a slot's designs/metrics/Pareto front, judge whether a fill improved it. Use before dispatching work and again afterwards to see what changed.
Skill Claude CodeCodex
Technology PPA (e.g. asap7) for stored slot designs — measure-and-annotate in one tool op so the DB can select on metric= , or --dry-run to just see the numbers. Minutes per design; score finalists, not every candidate.
At most 3 mods per repository are shown here, and a mod shipped inside a plugin is left to that plugin's page — the rest are on their repository pages: