rohd-rtl-gotchas

ROHD RTL Gotchas

Overview

ROHD (Rapid Open Hardware Development, Dart RTL) plus rohd_bridge and rohd_hcl have a handful of sharp edges that produce cryptic errors at build or sim setup, far from the actual cause. These are the ones that cost real hours on River and Harbor.

Core principle: Most of these surface as a hierarchy-rule violation or a "Bad state: No element" hang, and the fix is almost never where the error points. Match the symptom below to the cause directly instead of debugging the stack trace.

When to Use

• A ROHD build throws "Violation of input/output rules" or inverts the hierarchy
• Sim hangs or throws "Bad state: No element" during Sequential setup
• Co-simulating a DUT against a behavioral model that shares a bidirectional net
• SystemVerilog emission references a module name that the emitted file doesn't define
• A RegisterFile read returns data a cycle off from what the FPGA will do

inout Co-Simulation Between Siblings Is Forbidden

ROHD's hierarchy checker rejects wiring two sibling modules through a shared bidirectional (inout/LogicNet) net that closes a loop (a SPI controller plus a behavioral SPI-flash model sharing spi_io). The error reads "should only communicate via inputs/inouts" and it may even invert the hierarchy (think the DUT contains its parent).

• For a testbench, avoid the bidirectional co-sim. Test a path that uses a plain unidirectional input instead (drive MISO procedurally in standard mode rather than the quad inout bus). The FSM, byte-order, and data-assembly logic is usually shared across modes, so you still cover it.
• If you must share an inout, pass the SAME LogicNet to both modules' addInOut (the ROHD inout-loopback idiom). Do not <= one onto the other. Two active drivers stay fragile; a parent harness beats top-level wiring.
• Blackbox primitives (DP16KD and friends) have no sim model, so FPGA-only memory paths can't be co-simulated at all. Verify the equivalent flop model instead, at the same latency (see below).