arm-sve

ARM SVE

Purpose

Guide agents through ARM Scalable Vector Extension (SVE/SVE2) programming: vector-length agnostic (VLA) code, predicate registers, SVE intrinsics via <arm_sve.h>, runtime vector length with svcnt, compiler flags, platform differences (Graviton3, Apple M4), and GDB debugging of SVE registers.

When to Use

• Writing high-performance SIMD on AArch64 servers (AWS Graviton3/4)
• Porting fixed-width NEON code to length-agnostic SVE
• Using predicate masks for loop tails instead of separate cleanup loops
• Auto-vectorizing with GCC/Clang -march=armv9-a+sve2
• Debugging SVE register state in GDB on hardware with SVE support
• Exploiting SVE2 dot product and crypto extensions

Workflow

1. SVE vs NEON

	NEON	SVE/SVE2
Vector width	Fixed (128-bit)	Scalable (128–2048 bits, hardware dependent)
Predication	Limited	Full predicate registers P0–P15
Portability across ARM CPUs	Same width everywhere	VLA — adapts to hardware VL
Apple Silicon	Always available	M4+ has SVE2

2. Predicate and VLA concepts

SVE registers
├── Z0–Z31  — scalable vector data registers
└── P0–P15  — predicate (mask) registers

Vector Length (VL) — determined at runtime per CPU
svcntb() → bytes per vector
svcntw() → 32-bit elements per vector

Code written once runs at full width on any SVE-capable CPU.

3. SVE intrinsics example

#include <arm_sve.h>
#include <stddef.h>

void saxpy_sve(float *y, const float *x, float alpha, size_t n) {
    svbool_t pg = svwhilelt_b32(0, n);
    size_t i = 0;

    do {
        svfloat32_t vx = svld1_f32(pg, &x[i]);
        svfloat32_t vy = svld1_f32(pg, &y[i]);
        vy = svmla_n_f32_x(pg, vy, vx, alpha);  // y += alpha * x
        svst1_f32(pg, &y[i], vy);

        i += svcntw();  // advance by vector length in 32-bit elements
        pg = svwhilelt_b32(i, n);
    } while (svptest_any(svptrue_b32(), pg));
}

gcc -march=armv9-a+sve2 -O3 -o saxpy saxpy.c