stm32-baremetal

STM32 Bare-Metal (CMSIS, No HAL)

Purpose

Guide agents through a minimal STM32 bare-metal project using CMSIS device headers and startup code only — no STM32 HAL — covering clock setup, linker script integration, peripheral register access, and a reproducible build layout for STM32F/G/H/L families.

When to Use

• Starting STM32 firmware without Cube HAL dependency
• Porting vendor examples to register-level drivers
• Integrating with skills/baremetal/baremetal-startup and skills/embedded/linker-scripts
• Debugging clock or flash placement issues on STM32
• Teaching register-level STM32 before RTOS or Zephyr

Workflow

1. Minimal project layout

stm32-bare/
├── startup_stm32f407xx.s   # vector table + Reset_Handler
├── system_stm32f4xx.c      # SystemInit(), SystemCoreClockUpdate()
├── stm32f407xx.h           # CMSIS (from ST pack or copy)
├── linker.ld               # FLASH/RAM regions
├── main.c
└── Makefile

Use CMSIS-Core (core_cm4.h) and device header from ST CMSIS pack or open-source packs (e.g. stm32-cmsis-device-f4).

2. Clock configuration (RCC)

STM32 requires explicit HSE/HSI and PLL setup before high-speed peripherals:

/* system_stm32f4xx.c — simplified PLL from 8 MHz HSE */
void SystemInit(void)
{
    RCC->CR |= RCC_CR_HSEON;
    while (!(RCC->CR & RCC_CR_HSERDY)) {}

    RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | (8 << 0) | (336 << 6) | (0 << 16) | (7 << 24);
    RCC->CFGR   |= RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV1 | RCC_CFGR_HPRE_DIV1;
    RCC->CR     |= RCC_CR_PLLON;
    while (!(RCC->CR & RCC_CR_PLLRDY)) {}

    FLASH->ACR = FLASH_ACR_LATENCY_5WS;
    RCC->CFGR  |= RCC_CFGR_SW_PLL;
    while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}

    SystemCoreClockUpdate();
}

Always match FLASH_ACR wait states to voltage scale and SYSCLK per reference manual table.

3. Enable peripheral clock before MMIO

#define RCC_AHB1ENR_GPIOAEN (1U << 0)

static inline void gpioa_clock_enable(void)
{
    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
    (void)RCC->AHB1ENR; /* AHB read-after-write — required on STM32 */
}