design-logic-circuit

Design Logic Circuit

Translate a functional specification into a combinational logic circuit by defining inputs and outputs, deriving a minimal Boolean expression, mapping it to a gate-level schematic, optionally converting to a universal gate basis (NAND-only or NOR-only), and verifying correctness through exhaustive simulation against the original truth table.

When to Use

• Implementing a Boolean function as a physical or simulated gate network
• Designing standard combinational building blocks (adders, multiplexers, decoders, comparators)
• Converting an arbitrary gate network to NAND-only or NOR-only form for manufacturing constraints
• Teaching or reviewing digital logic design from specification to schematic
• Preparing the combinational datapath components needed by build-sequential-circuit or simulate-cpu-architecture

Inputs

• Required: Functional specification -- one of: truth table, Boolean expression, verbal description of input/output behavior, or a standard block name (e.g., "4-bit ripple-carry adder")
• Required: Target gate library -- unrestricted (AND/OR/NOT), NAND-only, NOR-only, or a specific standard cell library
• Optional: Optimization goal -- minimize gate count, minimize propagation delay (critical path), or minimize fan-out
• Optional: Maximum fan-in constraint (e.g., 2-input gates only)
• Optional: Don't-care conditions for inputs that will never occur

Procedure

Step 1: Specify Circuit Function

Define the circuit's interface and behavior completely before any synthesis:

1. Input signals: List all input signals with their names, bit widths, and valid ranges. For multi-bit inputs, specify bit ordering (MSB-first or LSB-first).
2. Output signals: List all output signals with their names and bit widths.
3. Truth table: Write the complete truth table mapping every input combination to the corresponding outputs. For circuits with many inputs, express the function algebraically or as a set of minterms/maxterms instead.
4. Don't-care conditions: Identify input combinations that cannot occur in practice (e.g., BCD inputs 1010-1111) and mark them as don't-cares.
5. Timing requirements: Note any propagation delay constraints, though combinational circuits have no clock -- timing here refers to worst-case gate delay through the critical path.