Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add zhaixin244-wq/fnw --skill chip-sdc-generatorgit clone --depth 1 https://github.com/zhaixin244-wq/fnwWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/zhaixin244-wq/fnw/chip-sdc-generator)<a href="https://agentmods.dev/skills/zhaixin244-wq/fnw/chip-sdc-generator"><img src="https://agentmods.dev/badge/skills/zhaixin244-wq/fnw/chip-sdc-generator/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/zhaixin244-wq/fnw/chip-sdc-generator"><img src="https://agentmods.dev/badge/skills/zhaixin244-wq/fnw/chip-sdc-generator.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00080 | $0.05390 |
| Opus 5 | $0.00040 | $0.02695 |
| Sonnet 5 | $0.00016 | $0.01078 |
| Haiku 4.5 | $0.00008 | $0.00539 |
Grade A, and why
chip-sdc-generator scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 9d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 449 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Chip SDC Generator
任务
根据 FS 功能规格书和微架构文档，生成完整的 SDC 时序约束文件。采用参数化模板方法，覆盖时钟定义、I/O 约束、设计规则、时序例外、面积/功耗约束全部类别。
与 chip-impl-sdc-sva 的区别：chip-impl-sdc-sva 是实现流水线中的快速 SDC 生成（仅从微架构 §6 提取基础时钟约束）；chip-sdc-generator 是独立的、全量 SDC 生成 skill，从 FS 提取完整约束需求，输出生产级 SDC 文件。
与 chip-sta-analyst 的关系：chip-sta-analyst 负责综合执行和时序分析；chip-sdc-generator 为其提供输入 SDC 文件。当用户需要"综合+时序分析"时，先用 chip-sdc-generator 生成 SDC，再交由 chip-sta-analyst 执行。
输入
| 输入 | 来源 | 必需 | 说明 |
|---|---|---|---|
| FS 文档 | {module}_work/ds/doc/fs/{module}_FS_v{X}.md |
是 | 时钟域、接口定义、PPA 指标、时序例外 |
| 微架构文档 | {module}_work/ds/doc/ua/{module}_*_microarch_v{X}.md |
否 | 关键路径分析、FIFO 参数、子模块时序 |
| RTL 文件 | {module}_work/ds/rtl/*.v |
否 | 端口列表自动提取（辅助） |
| 外部器件规格 | 用户提供或 FS §13 假设条件 | 否 | I/O delay 精确计算依据 |
知识检索
执行前必须完成以下 Wiki 检索（按需）：
wiki/concepts/SDC-Generation-Methods.md— 4 种生成方法和模板参考wiki/concepts/SDC-Best-Practices.md— 编写顺序、常见陷阱、验证清单wiki/questions/Research SDC文件生成规则与方法.md— 综合研究（工具链、经验参数）wiki/eda/synopsys/design-compiler/dc-constraints.md— DC 工具 SDC 编写指南（如使用 DC）wiki/eda/synopsys/primetime/pt-constraints.md— PT 约束编写指南（如使用 PT）
执行步骤
Phase 0：前置检查
- 用
Glob搜索{module}_work/ds/doc/fs/*FS*.md获取 FS 文档 - 若 FS 不存在，暂停并提示用户先完成 FS 编写
- 用
Glob搜索{module}_work/ds/doc/ua/*microarch*.md获取微架构文档（可选） - 用
Glob搜索{module}_work/ds/rtl/*.v获取 RTL 文件列表（可选，用于端口提取）
Phase 1：约束信息提取
从 FS 文档中提取以下信息：
| 提取项 | FS 来源 | 用途 |
|---|---|---|
| 时钟域定义 | §9 时钟与复位 | create_clock |
| 时钟频率 | §9 + §8.1 性能指标 | -period 参数 |
| PLL/分频器 | §9 + §5 子模块 | create_generated_clock |
| 时钟域关系 | §9 + §7 CDC | set_clock_groups |
| I/O 端口列表 | §6 顶层接口定义 | set_input/output_delay |
| 接口协议 | §6.1 接口列表 | I/O delay 精确建模 |
| PPA 指标 | §8 | 设计规则约束值 |
| 最大频率 | §8.1 | 时钟周期 |
| 功耗预算 | §8.2 | set_max_dynamic_power |
| 面积预算 | §8.3 | set_max_area |
| 设计约束 | §13 | 工艺节点、总线协议 |
| 时序例外 | §4.4 + §5.3 | set_false_path / set_multicycle_path |
| 复位策略 | §9 | 复位路径约束 |
| 异常处理 | §6.4 + §4.4 | 超时路径约束 |
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 9d ago First seen · 449 lines · 80 tokens per session scan A edf1d06f2a39
chip-sdc-generator is a skill published in the GitHub repository zhaixin244-wq/fnw (29 stars, last pushed 3mo ago), licensed MIT. It adds 80 tokens to every session and 5,390 once invoked, about $0.0004 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-09-03.
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