Autonomous iterative research loop. Takes a topic, runs web searches, fetches sources, synthesizes findings, and files everything into the wiki as structured pages. Based on Karpathy's autoresearch pattern: program.md configures objectives and constraints, the loop runs until depth is reached, output goes directly…
Visual layer of the wiki. Add images, text cards, PDFs, and wiki pages to Obsidian canvas files with auto-positioning inside zones. Integrates with /banana for image capture. Triggers on: /canvas, canvas new, canvas add image, canvas add text, canvas add pdf, canvas add note, canvas zone, canvas list, canvas from…
A selector for choosing a hardware arbitration strategy: fixed priority, round-robin, or weighted round-robin. Arbitration decides which competing channel gets access to a shared resource.
A planner for distributing system-level PPA targets across chip submodules. PPA means performance, power, and area; the planner also checks whether the submodule budgets add up to the system target.
A design assistant for clock-domain crossing (CDC), the safe movement of signals between parts of a chip that use different clocks. It identifies clock domains and recommends ways to synchronise control signals, data, pulses, and resets.
A workspace initializer for chip-design projects. It creates a standard directory tree for design files and verification files, including specifications, RTL code, libraries, test plans, and reports.
A design-space exploration assistant for chip hardware. It compares design choices such as pipeline depth, parallelism, cache size, bus width, frequency, and voltage using area, performance, and power estimates.
A diagram-making guide for chip designs, covering module block diagrams, timing diagrams, and state-machine diagrams. It uses D2, Wavedrom, and, when needed, Mermaid to produce PNG images.
A scoring tool for functional specifications, microarchitecture documents, and RTL code in chip projects. It rates quality across multiple criteria, checks consistency between related documents, and produces improvement suggestions.
A skill for designing the structure of microarchitecture specifications for chip modules. It creates a standard document outline with sections such as interfaces, internal design, performance, risks, and hardware implementation guidance.
A delivery checklist for RTL implementation work. RTL is the hardware description code used to design digital circuits, while linting, synthesis, and simulation check its quality and behavior.
A pre-coding checklist for checking whether an RTL implementation has the required architecture documents, coding rules, reusable-module list, protocol documents, and constraints.
A planning guide for organizing an RTL hardware module from microarchitecture documents. RTL is code that describes digital circuits, and microarchitecture documents specify how those circuits should be built.
A workflow for developing multiple RTL hardware modules in parallel. RTL is code that describes how digital circuits operate, and a submodule is one part of a larger chip design.
A quality-check procedure for RTL code, the hardware-description code used to design digital circuits. It runs lint checks and synthesis, which tests whether the design can be built into hardware and estimates its size.
A workflow for writing RTL, the hardware description code used to build chip circuits, for individual chip submodules. It covers data paths, control logic, reusable building blocks, and module connections based on a fixed architecture.
A guide for generating timing constraints, hardware assertions, and a testbench for RTL designs. SDC files describe timing requirements, SVA assertions express expected behavior, and a testbench drives and checks the design.
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+2 3mo agoA78 tokens
originalMIT
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