amoslee2026

amoslee2026/Babel

Skill Claude Code

A hardware-signal analysis tool that follows a signal from its source to its destination across module levels and checks whether it crosses clock domains. A clock-domain crossing happens when a signal moves between parts of a chip running on different clocks.

amoslee2026/Babel

Skill Claude CodeCodex

A placeholder skill entry with no specific subject, capabilities, or workflow described.

amoslee2026/Babel

Command Claude Code

A command that extracts structured test points from MAS, verifplanseed, or verificationplan files into JSON and Markdown. The output describes checks that later tools can turn into hardware tests.

amoslee2026/Babel

Command Claude Code

A command that creates a per-module SystemVerilog testbench harness from test points and RTL ports. The harness includes basic simulation structure, coverage setup, and lint support.

amoslee2026/Babel

Command Claude Code

A command that turns test points into executable SystemVerilog test cases, a test registry, and a script for running them. SystemVerilog is a language commonly used to describe and test digital hardware.

amoslee2026/Babel

Skill Claude Code

A tool that extracts structured test points from verification plans into JSON and Markdown files. These test points can be used by tools that create hardware testbenches and test cases.

amoslee2026/Babel

Skill Claude Code

A tool that creates a SystemVerilog testbench harness for each hardware module from test points and RTL ports. A testbench is code that drives a hardware design and checks its results.

amoslee2026/Babel

Skill Claude Code

A tool that converts structured test points into executable SystemVerilog tasks, test registries, documentation, and run scripts. It creates targeted, boundary, reset, and CDC variations where the test-point category calls for them; CDC means clock-domain crossing.