make

GNU Make

Purpose

Guide agents through idiomatic Makefile patterns for C/C++ projects: phony targets, pattern rules, automatic dependency generation, and common build idioms.

Triggers

• "How do I write a Makefile for my C project?"
• "My Makefile rebuilds everything every time"
• "How do I add dependency tracking to Make?"
• "What does $@, $<, $^ mean?"
• "I'm getting 'make: Nothing to be done for all'"
• "How do I convert my shell compile script to a Makefile?"

Workflow

1. Minimal correct Makefile for C

CC      := gcc
CFLAGS  := -std=c11 -Wall -Wextra -g -O2
LDFLAGS :=
LDLIBS  :=

SRCS    := $(wildcard src/*.c)
OBJS    := $(SRCS:src/%.c=build/%.o)
TARGET  := build/prog

.PHONY: all clean

all: $(TARGET)

$(TARGET): $(OBJS)
	$(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)

build/%.o: src/%.c | build
	$(CC) $(CFLAGS) -c -o $@ $<

build:
	mkdir -p build

clean:
	rm -rf build

Automatic variables:

• $@ — target name
• $< — first prerequisite
• $^ — all prerequisites (deduplicated)
• $* — stem (the % part in a pattern rule)
• $(@D) — directory part of $@

2. Automatic dependency generation

Without this, changing a header doesn't trigger a rebuild of .c files that include it.

CC      := gcc
CFLAGS  := -std=c11 -Wall -Wextra -g -O2
DEPFLAGS = -MMD -MP            # -MMD: generate .d file; -MP: phony targets for headers

SRCS    := $(wildcard src/*.c)
OBJS    := $(SRCS:src/%.c=build/%.o)
DEPS    := $(OBJS:.o=.d)
TARGET  := build/prog

.PHONY: all clean

all: $(TARGET)

$(TARGET): $(OBJS)
	$(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)

build/%.o: src/%.c | build
	$(CC) $(CFLAGS) $(DEPFLAGS) -MF $(@:.o=.d) -c -o $@ $<

-include $(DEPS)    # '-' ignores errors on first build (no .d files yet)

build:
	mkdir -p build

clean:
	rm -rf build

3. Pattern rules cheatsheet

# Compile C
%.o: %.c
	$(CC) $(CFLAGS) -c -o $@ $<

# Compile C++
%.o: %.cpp
	$(CXX) $(CXXFLAGS) -c -o $@ $<

# Generate assembly
%.s: %.c
	$(CC) $(CFLAGS) -S -o $@ $<

# Run a tool on each file
build/%.processed: src/%.raw | build
	mytool $< > $@