build-sequential-circuit

Build Sequential Circuit

Design a sequential logic circuit by identifying the required memory and state type, constructing a state diagram and transition table, deriving excitation equations for the chosen flip-flop type, implementing the circuit at the gate level using flip-flops and combinational logic, and verifying correctness through timing diagram analysis and state sequence simulation.

When to Use

• A circuit must remember past inputs or maintain internal state across clock cycles
• Designing counters (binary, BCD, ring, Johnson), shift registers, or sequence detectors
• Implementing a finite state machine (Mealy or Moore) from a state diagram or regular expression
• Adding clocked storage elements to a combinational datapath (registers, pipeline stages)
• Preparing stateful components for the simulate-cpu-architecture skill (register file, program counter, control FSM)

Inputs

• Required: Behavioral specification -- one of: state diagram, state table, timing diagram, regular expression to detect, or verbal description of the desired sequential behavior
• Required: Clock characteristics -- edge-triggered (rising/falling) or level-sensitive; single clock or multi-phase
• Optional: Flip-flop type preference (D, JK, T, or SR)
• Optional: Reset type -- synchronous, asynchronous, or none
• Optional: Maximum state count or bit width constraint
• Optional: Timing constraints (setup time, hold time, maximum clock frequency)

Procedure

Step 1: Identify Memory and State Requirements

Determine what the circuit needs to remember and how many distinct states it requires:

1. State enumeration: List all distinct states the circuit must be in. For a sequence detector, each state represents the progress through the target sequence. For a counter, each state is a count value.
2. State encoding: Choose a binary encoding for the states.
   • Binary encoding: Uses ceil(log2(N)) flip-flops for N states. Minimizes flip-flop count.
   • One-hot encoding: Uses N flip-flops, one per state. Simplifies next-state logic at the cost of more flip-flops.
   • Gray code encoding: Adjacent states differ in exactly one bit. Minimizes transient glitches during transitions.
3. Input and output classification: Identify primary inputs (external signals), primary outputs, and internal state variables (flip-flop outputs). For Mealy machines, outputs depend on both state and input. For Moore machines, outputs depend only on state.
4. Flip-flop type selection: Choose based on the design's needs.
   • D flip-flop: Simplest -- next state equals the D input. Best default choice.
   • JK flip-flop: Most flexible -- J=K=1 toggles. Good for counters.
   • T flip-flop: Toggle type -- changes state when T=1. Natural for binary counters.
   • SR latch/flip-flop: Set-Reset -- avoid the S=R=1 condition. Rarely preferred for new designs.