Getting it into your agent
It runs from inside its repository, so the clone comes first — what it calls does not travel with the file alone.
git clone --depth 1 https://github.com/vibeic/vibe-icnpx agentmods add skills/vibeic/vibe-ic/analog-hardmacro-genWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/vibeic/vibe-ic/analog-hardmacro-gen)<a href="https://agentmods.dev/skills/vibeic/vibe-ic/analog-hardmacro-gen"><img src="https://agentmods.dev/badge/skills/vibeic/vibe-ic/analog-hardmacro-gen/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/vibeic/vibe-ic/analog-hardmacro-gen"><img src="https://agentmods.dev/badge/skills/vibeic/vibe-ic/analog-hardmacro-gen.svg" alt="Reviewed on agentmods" width="80" height="20"></a>- NVIDIA SkillSpector pass
What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00069 | $0.02126 |
| Opus 5 | $0.00034 | $0.01063 |
| Sonnet 5 | $0.00014 | $0.00425 |
| Haiku 4.5 | $0.00007 | $0.00213 |
Grade A, and why
analog-hardmacro-gen scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 7d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 160 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Analog Hardmacro Gen
Takes a verified analog block (SPICE corner sweep passed, optionally hardware-verified) and produces the four deliverables that digital PnR (OpenROAD) needs to integrate it alongside standard cells.
When to use
- Step A7 of the analog track
- After
analog-extraction-resimconfirms post-layout specs are acceptable - When the user says "package this analog block for digital integration"
Inputs
analog/<block>/corner_results.json— worst-case timing from SPICEanalog/<block>/layout.mag— Magic layout (or generate viaeda_analog_layout)analog/<block>/spec.json— port definitions- PDK (gf180 or sky130)
Four deliverables
Deliverable PRESENCE + non-degeneracy is enforced deterministically:
programs/analog_hardmacro_check.py(all 4 files exist; LEF has MACRO/PIN, LIB has cell, V has module) andprograms/analog_liberty_nonzero_delay_check.py(the "no zero-delay Liberty" rule — area-only / all-zero.lib=> FAIL; a propagation arc slower than the design's declared SDC/L8 clock period => FAIL). Cross-file pin-name equality is enforced byprograms/analog_hardmacro_pinname_consistency_check.py.
1. GDS (hardmacro/<block>/<block>.gds)
- NOT YOUR JOB — a program does this.
programs/analog_hardmacro_gds_emit.pystreamsphase3/analog/<block>/layout.magout tophase3/analog/hardmacro/<block>/<block>.gdswith Magic, against the technology the layout's owntechline names.analog_one_shot_runnerinvokes it atA8_hardmacro_gen, before the A8 checks. It is deliberately NOT wired into A8's flow gate:flow_compliance_checkis the acceptance auditor, and an auditor that writes a declaredrequired_outputinto the project it audits certifies its own output. Do not hand-author a.gds. - Its TCL is
magic_port_extract_emit.build_gds_write_tcl— the same fixedload / select top cell / gds writetemplate the extraction path uses. Between v0.1.114 and 2026-07 that emitter had no caller at all, which is why A8 declared a layout no run produced. - Honest contract: rc=2 when no container/Magic/magicrc for that technology is
reachable, rc=1 when Magic runs and the result carries no geometry (the
hollow file is deleted, never left where a presence check would count it),
and a deterministic-stub
layout.magis skipped so the PASS_WITH_STUB tier is untouched. - If the block has no
layout.magyet, runeda_analog_layout(A5) first — the producer names that as its skip reason rather than inventing geometry.
What ships with it
2 files beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 7d ago Changed · +14 lines c39bb7987758
- 11d ago First seen · 146 lines · 69 tokens per session scan A a960494ea017
analog-hardmacro-gen is a skill published in the GitHub repository vibeic/vibe-ic (23 stars, last pushed today), licensed Apache-2.0. It adds 69 tokens to every session and 2,126 once invoked, about $0.0003 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
Other skills, from other repositories
analog-netlist-crawl
Crawl and analyze post-layout parasitic netlists without running SPICE. Answers "what's the effective resistance from node A to node B across this massive R mesh?", "inside the VREFN mesh, which device pins are electrically farthest apart?", "which nets have the worst coupling?", "where does settling bottleneck?" — by…
analog-verify
Pre-simulation review and Spectre simulation verification for analog circuits. Reviews circuit netlist and testbench, runs simulation, produces margin report. Use after analog-design completes a netlist.
analog-design
Transistor-level circuit design for one analog sub-block. Produces Spectre netlist with hand-calculation rationale. Use when designing a specific circuit block after architecture is defined.
analog-pipeline
MANDATORY — MUST load this skill when the user mentions: OTA, ADC, PLL, comparator, bandgap, LDO, amplifier, opamp, or any analog/mixed-signal IC design task. Full analog design pipeline: spec -> architecture -> design -> verify -> deliver. Orchestrates analog-decompose, analog-behavioral, analog-design…
analog-audit
Audit analog circuit netlists for correctness, quality, and risks. Supports both pre-layout (schematic) and post-layout (extracted) netlists. Post-layout mode filters massive parasitic netlists before auditing. Works without EDA. TRIGGER on: "audit", "review netlist", "check this circuit", "design review"…
analog-decompose
Architect Phase 1: decompose top-level analog spec into sub-block specs. Use when starting a new analog design to select architecture, allocate budgets, define sub-block specs, write testbenches, and create verification plans.