Getting it into your agent
It runs from inside its repository, so the clone comes first — what it calls does not travel with the file alone.
git clone --depth 1 https://github.com/vibeic/vibe-icnpx agentmods add skills/vibeic/vibe-ic/testbench-genWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/vibeic/vibe-ic/testbench-gen)<a href="https://agentmods.dev/skills/vibeic/vibe-ic/testbench-gen"><img src="https://agentmods.dev/badge/skills/vibeic/vibe-ic/testbench-gen/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/vibeic/vibe-ic/testbench-gen"><img src="https://agentmods.dev/badge/skills/vibeic/vibe-ic/testbench-gen.svg" alt="Reviewed on agentmods" width="80" height="20"></a>- NVIDIA SkillSpector pass
What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00185 | $0.04015 |
| Opus 5.5 | $0.00074 | $0.01606 |
| Sonnet 5.5 | $0.00037 | $0.00803 |
| Haiku 4.5 | $0.00018 | $0.00402 |
Grade A, and why
testbench-gen scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 4d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 251 lines — stays where its author put it; the contents beside it link to each section on GitHub.
testbench-gen — deterministic professional testbench generation
The canonical flow's Step 4 (Simulation) derives a professional, high-coverage
testbench from the Phase-1 layers — never a hand-waved skeleton. The load-bearing
work is a PROGRAM: programs/professional_tb_gen.py (exposed as MCP tool
eda_professional_tb). This skill is the judgment layer around it.
What the program does (program-first)
professional_tb_gen.py <project> reads the project's phase1/generated_docs/L*.json
and emits, under phase2/stage1/sim_professional/<top>/:
tb_<top>.py— a cocotb testbench: clock/reset from L8/L9, a reference model, a SCOREBOARD, functional coverage (cocotb-coverage covergroups), and a directed-corner + constrained-random stimulus loop.<top>_coverage_model.json(an L28 coverage model),<top>_assertions.sva(an L29 assertion set), a cocotbMakefile, andverification_plan.json.
It combines open-source frameworks rather than re-inventing them: cocotb
(TB base) + cocotb-coverage (functional coverage + constrained-random) +
Verilator/Icarus (sim) + an SVA bind for Verilator/SymbiYosys. Add
cocotb-coverage to the runtime (see mcp-eda/INSTALL_GUIDE.md).
The reference-model strategy — 3 tiers (honest, never a vacuous pass)
- Closed-form (arithmetic primitives
c = a OP b): reusesarith_oracle_tb_gen.compute_golden— the single source of truth. - Bounded-latency streaming scoreboard (serial datapaths — one parallel
operand + a 1-bit serial operand + a 1-bit serial result, e.g. a bit-serial
multiplier): the scoreboard AUTO-DERIVES the output
(latency, bit_order)from a calibration vector, then checks every vector against the closed-form reference. This closes the serial-datapath DEFER thatarith_oracle_tb_genpunts on entirely (proven: spm bit-serial multiplier, 208/208 vs(x*y) mod 2^N,order=lsb latency=1auto-derived). - Reference hook (classes with no closed form — CPU/SoC/DSP): the generated
TB emits a clearly-marked
reference_modelhook thatTestSkips until filled — NEVER a silent vacuous pass. The judgment layer (this skill / spec-to-refmodel) fills it from L10 vectors or a spec-derived model, with the program-vs-AI cross-check (dual-track convergence).
What ships with it
2 files beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 4d ago Changed · +21 lines 9fbaa2e34709
- 8d ago Changed · +14 lines 21f531a88e5e
- 9d ago Changed · +27 lines 931067ee78bb
- 15d ago Changed · +14 lines a3e54ebe02c3
- 16d ago Changed · +43 lines 855754743d33
- 1mo ago First seen · 132 lines · 185 tokens per session scan A eb196a2714e3
testbench-gen is a skill published in the GitHub repository vibeic/vibe-ic (28 stars, last pushed today), licensed Apache-2.0. It adds 185 tokens to every session and 4,015 once invoked, about $0.0007 per session on Opus 5.5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-09-03.
Other skills, from other repositories
analog-verify
Pre-simulation review and Spectre simulation verification for analog circuits. Reviews circuit netlist and testbench, runs simulation, produces margin report. Use after analog-design completes a netlist.
pcb-lint
Run a battery of PCB design-hygiene checks against the board open in EasyEDA Pro, through the easyeda MCP tools, and produce a scored report. Use when the user says "/pcb-lint", "lint the board", "run PCB checks", "check my layout", "is this board ready to fab?", or finishes a PCB layout iteration and is about to…
step6-verify
Step 6 · Per-module simulation verification (amnesia audit → human-confirmed plan → autonomous local-fix loop → full re-verify; escalate only when local options are exhausted).
boardrepo
Read and review real PCB projects on BoardRepo. Search published hardware designs, open a board's schematic connectivity, bill of materials and files, run KiCad's DRC and ERC, and check a design against a fabrication house's limits. Use whenever the user names a BoardRepo board or URL, asks to find a published board…
analog-netlist-crawl
Crawl and analyze post-layout parasitic netlists without running SPICE. Answers "what's the effective resistance from node A to node B across this massive R mesh?", "inside the VREFN mesh, which device pins are electrically farthest apart?", "which nets have the worst coupling?", "where does settling bottleneck?" — by…
analog-design
Transistor-level circuit design for one analog sub-block. Produces Spectre netlist with hand-calculation rationale. Use when designing a specific circuit block after architecture is defined.