Skill Claude CodeCodex
A workflow for writing RTL, the hardware description code used to build chip circuits, for individual chip submodules. It covers data paths, control logic, reusable building blocks, and module connections based on a fixed architecture.
Skill Claude CodeCodex
A guide for generating timing constraints, hardware assertions, and a testbench for RTL designs. SDC files describe timing requirements, SVA assertions express expected behavior, and a testbench drives and checks the design.
Skill Claude CodeCodex
A checklist-driven review tool for RTL implementation, which is code describing digital hardware such as chips or circuits. It checks implementation files alongside lint, synthesis, and microarchitecture information before delivery.
Skill Claude CodeCodex
A specification writer for module interface contracts in chip design, describing how hardware modules exchange signals and data.
Skill Claude CodeCodex
A hardware-code checking guide for RTL, the code used to describe digital circuits. It selects an available checking tool, such as Verilator, Verible, Yosys, or SpyGlass, and produces a lint report.
Skill Claude CodeCodex
Use when processing vc-spyglass lint log output to resolve violations. Maps lint rules to JMTAG execution levels, proposes RTL fixes or generates waive files. Triggered by keywords like spyglass, lint log, lint violation, JMTAG, waive file, lint rules.
Skill Claude CodeCodex
A design guide for reducing power use in chip modules by dividing the chip into power areas and defining how each area shuts down, retains data, and restarts.
Skill Claude CodeCodex
A workflow for creating and checking microarchitecture diagrams, which show how parts of a chip are organised and communicate. It covers D2 diagrams, WaveDrom timing diagrams, and interface diagrams.
Skill Claude CodeCodex
A diagram generator for chip designs that turns D2 text files into PNG images. It supports architecture, data-flow, and state-machine diagrams, using D2’s dagre layout.
Skill Claude CodeCodex
A generator for PNG port diagrams from Verilog module declarations, where Verilog is a language for describing digital hardware. Each diagram shows the module in the center, input signals on the left, output signals on the right, and signal widths and directions.
Skill Claude CodeCodex
A marketplace containing development tools and plugins for the Frappe framework, a platform used to build business applications. The listed collection includes a Frappe application manager.
Skill Claude CodeCodex
A formatter for PPA specification tables, where PPA means performance, power, and area. It organizes measurements such as latency, power use, chip size, and quality, while recording units, targets, budgets, estimates, and constraints.