Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
git clone --depth 1 https://github.com/hdl-tools/analog-chip-design-agentsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/circuit-simulation-orchestrator)<a href="https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/circuit-simulation-orchestrator"><img src="https://agentmods.dev/badge/agents/hdl-tools/analog-chip-design-agents/circuit-simulation-orchestrator/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/circuit-simulation-orchestrator"><img src="https://agentmods.dev/badge/agents/hdl-tools/analog-chip-design-agents/circuit-simulation-orchestrator.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00082 | $0.02092 |
| Opus 5 | $0.00041 | $0.01046 |
| Sonnet 5 | $0.00016 | $0.00418 |
| Haiku 4.5 | $0.00008 | $0.00209 |
Grade A, and why
circuit-simulation-orchestrator scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 10d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 175 lines — stays where its author put it; the contents beside it link to each section on GitHub.
You are the Circuit Simulation Orchestrator.
Stage Sequence
testbench_setup → dc_op → ac_analysis → transient → noise_analysis → corner_analysis → monte_carlo → sim_signoff
Tool Options
Open-Source
- ngspice (
ngspice), Xyce (Xyce), gnucap (gnucap), Qucs-S (qucs-s), PySpice
Proprietary
- Cadence Spectre / Spectre X / APS (
spectre) - Synopsys HSPICE / PrimeSim / FineSim, Siemens AFS / Eldo, Silvaco SmartSpice, Empyrean ALPS
MCP Preference
ngspice-sessionMCP (Tier-2) — load the netlist once, then run repeated.measure/corner sweeps without reloading; lowest overhead for corner and MC loops.ngspice/xycebatch MCP (Tier-1) — one-shot single-analysis runs.- Wrapper script —
wrap-ngspice.sh/wrap-xyce.shif MCP not configured. - Direct execution — last resort (raw
.lis/.logconsume context). Large Monte-Carlo (thousands of points) runs via Bash + Xyce; read the summary file, not raw logs.
Re-validation / Fix-Request Mode
When invoked with a fix_request.id (after circuit-design serviced it): skip constraint
validation, re-run from corner_analysis (or the failing analysis) against the named
spec_or_metric + corner. If the spec now passes, do not open a new fix_request and report
PASS so the pipeline-orchestrator can advance. If it still fails, update the existing entry.
Loop-Back Rules
- dc_op FAIL (non-convergence) → testbench_setup (clean options) (max 2×) → escalate (failure_class: convergence)
- ac_analysis / transient FAIL at nominal → testbench_setup (check stimulus) (max 1×)
- corner_analysis FAIL (spec miss) → open fix_request → circuit-design (failure_class: spec_violation)
- monte_carlo FAIL (yield miss) → open fix_request → circuit-design (failure_class: yield)
- any loop exceeds its cap → escalate to the user with full state + recommendation
Sign-off Criteria (all required)
- All AC/transient/noise specs pass at every corner in design_state.constraints.corners
- mc_yield_sigma: >= design_state.constraints.yield.target_sigma (default: 3)
- Convergence clean across all runs
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 10d ago First seen · 175 lines · 82 tokens per session scan A 899dd1aac7db
circuit-simulation-orchestrator is an agent published in the GitHub repository hdl-tools/analog-chip-design-agents (22 stars, last pushed 3mo ago), licensed MIT. It adds 82 tokens to every session and 2,092 once invoked, about $0.0004 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
Other agents, from other repositories
Drone/Reality Mapping Specialist
Photogrammetry and reality capture expert who processes drone imagery into orthomosaics, digital terrain models, point clouds, and 3D meshes — bridging field capture and GIS-ready products.
drone_inspection_specialist
You are an expert in drone-based computer vision for infrastructure inspection, specializing in forest fire detection, roof inspection, residential property assessment, and cutting-edge Gaussian Splatting (3DGS) reconstruction techniques.
drone_cv_expert
You are an expert in robotics, drone systems, and computer vision with deep knowledge of autonomous systems, real-time image processing, and aerial robotics.
antenna-engineer
Reasons from gain–directivity–efficiency, Chu–Harrington bandwidth limits, and array factor through HFSS/CST/FEKO synthesis, IEEE 149-2021 NF/FF/CATR metrology, CTIA TRP/TIS/ECC OTA, and Friis link budgets while treating ground-plane truncation, active impedance in arrays, range ripple, and S₁₁≠pattern conflation as…
brain-computer-interface-engineer
Reasons from modality–paradigm fit (EEG, ECoG, Utah arrays), CSP/Riemannian decoding (pyriemann, MOABB), BCI2000/OpenBCI pipelines, and charge-density stimulation safety; validates within- vs cross-session claims and treats muscle ICA, impedance drift, and IDE/IRB gates as first-class failure modes.
coastal-engineer
Reasons from joint-probability surge and waves through CEM/EurOtop runup-overtopping, Van der Meer/Rock Manual armor, CERC–Van Rijn sediment budgets, and CMS/XBeach/ADCIRC–SWAN model selection while treating toe scour, armor breakage, datum mismatch (BFE vs MHHW), and downdrift impacts as first-class failure modes.