Getting it into your agent
This one installs as part of its plugin. Adding the marketplace and installing the plugin brings it with everything else the plugin ships.
/plugin marketplace add alivirgo/Major-AI-Skills/plugin install major-ai-skillsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/alivirgo/major-ai-skills/cadence-virtuoso)<a href="https://agentmods.dev/skills/alivirgo/major-ai-skills/cadence-virtuoso"><img src="https://agentmods.dev/badge/skills/alivirgo/major-ai-skills/cadence-virtuoso/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/alivirgo/major-ai-skills/cadence-virtuoso"><img src="https://agentmods.dev/badge/skills/alivirgo/major-ai-skills/cadence-virtuoso.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00036 | $0.02154 |
| Opus 5 | $0.00018 | $0.01077 |
| Sonnet 5 | $0.00007 | $0.00431 |
| Haiku 4.5 | $0.00004 | $0.00215 |
Grade A, and why
cadence-virtuoso scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured yesterday.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 152 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Cadence Virtuoso IC Design AI Skill Guide (Claude)
Overview & Engine Architecture
Cadence Virtuoso is the premier analog, RF, and mixed-signal integrated circuit (IC) design environment, built on the OpenAccess (OA) database standard. Virtuoso integrates transistor-level schematic capture, full-custom polygon layout, physical verification (DRC/LVS via Pegasus / PVS / Assura), parasitic extraction (Quantus QRC), and SPICE simulation via the Spectre Circuit Simulator. Automation is driven by the Lisp-based Cadence SKILL programming language and the OCEAN (Open Command Environment for Analysis) batch simulation framework. Claude operates as a Principal Analog IC Design Lead and Tapeout Verification Architect, specializing in SKILL layout automation, OCEAN PVT corner & Monte Carlo characterization, DRC/LVS debug, and OA database concurrency.
Cadence Virtuoso & Spectre Execution Stack
┌─────────────────────────────────────────────────────────────┐
│ Cadence Virtuoso Architecture │
│ │
│ Design Entry & OpenAccess Database │
│ ├── `cds.lib` Library Registry & OpenAccess (OA) Hierarchies│
│ ├── Virtuoso Schematic Editor (Transistor-Level Composer) │
│ └── Virtuoso Layout Suite (Full-Custom Sub-Micron Polygon) │
│ │
│ Simulation & Physical Verification Stack │
│ ├── Spectre / Spectre X FastSPICE Multi-Threaded Engine │
│ ├── OCEAN Batch Simulation Framework & SKILL API │
│ └── Pegasus / PVS Physical Verification (DRC, LVS, QRC) │
└─────────────────────────────────────────────────────────────┘
Operational Capabilities & Agent Directives
- OCEAN Batch Simulation Automation: Author robust OCEAN scripts (
.ocn) to execute multi-corner PVT sweeps (Process: TT/FF/SS/FS/SF, Voltage $\pm 10%$, Temperature $-40^\circ\text{C}$ to $125^\circ\text{C}$) and export bandwidth, phase margin, and slew rate metrics. - Cadence SKILL Programming: Write clean SKILL functions (
procedure(),dbCreateRect(),dbOpenCellViewByType()) for procedural layout generation, guard ring placement, and pin placement. - DRC / LVS Physical Verification Triage: Resolve complex layout-versus-schematic mismatches, short circuits, soft-check substrate taps, and antenna ratio violations.
- OpenAccess Lock & Environment Management: Diagnose and clean stale
.cdslckfile locks, configure~/.cdsinitstartup scripts, and resolve technology display definitions (display.drf).
What ships with it
2 files beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- yesterday Changed · -15 tokens per session 86e6acc4986e
- 7d ago First seen · 152 lines · 51 tokens per session scan A 8b7a1d000906
cadence-virtuoso is a skill published in the GitHub repository alivirgo/Major-AI-Skills (1 stars, last pushed today), licensed MIT. It adds 36 tokens to every session and 2,154 once invoked, about $0.0002 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-09-05.
Other skills, from other repositories
spec-to-rtl
MANDATORY entry point when designoneshotrunner.steprtlgen WAIVES with fallbackskill='spec-to-rtl'. This is invoked for every IC class with rtlgen=null in icclassregistry.json, which is the SOURCE OF TRUTH for that set and the thing the runner actually routes from -- at the time of writing the 11 such classes are…
analog-layout
Plan analog layout with matching, common-centroid, interdigitation, dummy devices, guard rings, and shielding. Use when the user says "analog layout", "matching layout", "common centroid", "dummies", "guard ring", "interdigitated", "current mirror layout", "differential pair layout".
layer-contract-doctrine
Read BEFORE authoring or revising an L-layer emitter, an L-layer schema field, or a layer gate. Answers the three questions no program can decide for you — WHICH of the 27 layers a given fact belongs in (the layer that CONSUMES it, not any layer that mentions it), WHETHER the thing you are specifying is structural…
open-benchmark-methodology
Mandatory for VerilogEval, VerilogEval-v2, VerilogEval-Human, CVDP, RTLLM, PyHDL-Eval, RTL-Repo, MetRex, ResBench, ChipAgentsBench, benchmark, pass@1, benchmark floor/defect, run/rerun/score benchmark, or interpreting benchmark results. Enforces one general product entry, clean-room blind evaluation, Program First…
catalog-glue-author
When designoneshotrunner.steprtlgen WAIVES rtlgen and ipcatalogquery has emitted matches, this skill pulls the matched open-source IP RTL into the project's canonical phase2/stage1/rtl/ directory and authors only the integration wrapper / chip-top + OpenLane config glue from L1-L27 spec. Replaces full-from-scratch…
drc-fix
Diagnose and fix Design Rule Check (DRC) violations in a layout or GDS. Use when the user says "fix DRC", "DRC clean", "resolve spacing errors", "my layout fails DRC", or shares a DRC report from Calibre, Klayout, or Magic.