A Claude Code plugin for process management from requirement sorting to delivery
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Skill Claude Code
A checklist-driven review tool for RTL implementation, which is code describing digital hardware such as chips or circuits. It checks implementation files alongside lint, synthesis, and microarchitecture information before delivery.
Skill Claude Code
A specification writer for module interface contracts in chip design, describing how hardware modules exchange signals and data.
Skill Claude Code needs its repo
A hardware-code checking guide for RTL, the code used to describe digital circuits. It selects an available checking tool, such as Verilator, Verible, Yosys, or SpyGlass, and produces a lint report.
Skill Claude Code
Use when processing vc-spyglass lint log output to resolve violations. Maps lint rules to JMTAG execution levels, proposes RTL fixes or generates waive files. Triggered by keywords like spyglass, lint log, lint violation, JMTAG, waive file, lint rules.
Skill Claude Code
A design guide for reducing power use in chip modules by dividing the chip into power areas and defining how each area shuts down, retains data, and restarts.
Skill Claude Code needs its repo
A workflow for creating and checking microarchitecture diagrams, which show how parts of a chip are organised and communicate. It covers D2 diagrams, WaveDrom timing diagrams, and interface diagrams.
Skill Claude Code needs its repo
A diagram generator for chip designs that turns D2 text files into PNG images. It supports architecture, data-flow, and state-machine diagrams, using D2’s dagre layout.
Skill Claude Code
A generator for PNG port diagrams from Verilog module declarations, where Verilog is a language for describing digital hardware. Each diagram shows the module in the center, input signals on the left, output signals on the right, and signal widths and directions.
Skill Claude Code
A marketplace containing development tools and plugins for the Frappe framework, a platform used to build business applications. The listed collection includes a Frappe application manager.
Skill Claude Code
A formatter for PPA specification tables, where PPA means performance, power, and area. It organizes measurements such as latency, power use, chip size, and quality, while recording units, targets, budgets, estimates, and constraints.
Skill Claude Code
A checker for verifying hardware module interfaces against bus protocols such as AXI, APB, CHI, and TileLink. These protocols define how chip modules exchange addresses, data, and control signals.
Skill Claude Code
A guide for assessing reliability risks in chip designs, including random memory or register bit flips, circuit aging, voltage drops, metal wear, heat, and power-related failures. It also considers protections such as error correction and redundant logic.
Skill Claude Code
A review checklist for chip functional specifications, microarchitecture documents, and RTL code. It checks interfaces, performance targets, timing, clock-domain crossings, low-power design, reliability, verification, and synthesizable code.
Skill Claude Code
A checker for common bugs in RTL, the hardware description code used to build digital circuits. It examines pipelines, state machines, input capture, interfaces, FIFOs, data widths, and resource conflicts.
Skill Claude Code
A generator for RTL coding rules and implementation guidance based on a chip's microarchitecture. RTL is hardware description code that defines the circuits to be synthesized, and the guidance covers clocks, resets, state machines, interfaces, scan testing, and assertions.
Skill Claude Code
A generator for SDC timing-constraint files, which tell chip design tools how clocks, inputs, outputs, exceptions, area, and power should be evaluated. It builds the constraints from functional specifications and microarchitecture documents.
Skill Claude Code
A hardware-design verification skill that checks RTL, the code used to describe digital circuits, for clock-domain crossing problems with Synopsys SpyGlass. Clock-domain crossing is the movement of signals between parts of a chip that use different clocks.
Skill Claude Code
An RTL review helper for SpyGlass CDC reports. It reads clock-domain crossing violations, ranks them, and suggests RTL fixes or creates waiver files for accepted findings.
Skill Claude Code
An RTL checker for reset-domain crossings using SpyGlass. A reset-domain crossing is a signal path between parts of a chip that use different reset domains.
Skill Claude Code
An RTL review helper for SpyGlass RDC reports. It reads reset-domain crossing violations, ranks them, and suggests RTL fixes or creates waiver files for accepted findings.
Skill Claude Code
An automation helper for running Yosys synthesis on Verilog RTL. Synthesis checks whether the hardware code can be built and estimates resources such as area and timing.
Skill Claude Code
A requirements traceability tool that links documented requirements to architecture decisions, interfaces, performance targets, and verification plans. An RTM, or Requirements Traceability Matrix, shows whether each requirement is covered.
Skill Claude Code
A document comparison tool for architecture specifications. It identifies interface, microarchitecture, performance, risk, and RTL-guidance changes, then assesses their downstream impact.
Skill Claude Code
Persistent per-project memory for Claude Code. Auto-loads project context on session start, tracks sessions with git activity, and writes to native memory. Commands run deterministic Node.js scripts — behavior is consistent across model versions.
At most 3 mods per repository are shown here, and a mod shipped inside a plugin is left to that plugin's page — the rest are on their repository pages: