Plans a KiCad PCB end to end when ONE run must both place and route it. Sequences the placement skill and the routing skill, and owns the rules that exist only when the two meet: that placement invalidates every downstream routed board, that a routing failure must be classified before it is retried, and that a…
Analyses a KiCad PCB's PLACEMENT and produces a placement plan. Measures whether the board should be placed or re-placed at all and decides from that measurement, detects an unplaced board, separates the parts whose position is a mechanical fact from the ones a search may move, reconstructs a damaged placement…
Analyzes a KiCad PCB file and creates a comprehensive routing plan. Examines components for fanout needs (BGA/QFN/QFP/PGA), identifies differential pairs, categorizes power/ground nets, and presents a step-by-step routing workflow with explanations.
Use when the user needs embedded hardware architecture, MCU/SoC selection, power tree design, interface planning, sensor/actuator selection, RF/connectivity, BOM risk assessment, PCB/layout constraints, schematic-ready proposals, validation plans, or hardware design review.
Create and verify Altium schematic symbols (.SchLib) and PCB footprints (.PcbLib) from datasheets and 2D drawings, as code. Use whenever a part library must be made, fixed, measured from a drawing, or checked. Triggers: "make a footprint", "create a symbol", "add this part to the library", "SchLib", "PcbLib"…
Altium PCB component placement — derive board size, decide rotation for main ICs and connectors, split zones, generate a 1:1 placement plan drawing, then inject real coordinates after approval, and check overlaps. Triggers: "PCB placement", "place the components", "how big should the board be", "board outline", "start…
Review an Altium schematic (.SchDoc) — find unconnected pins, missing footprint links and net errors, then judge each candidate against the datasheet before calling it a defect. Triggers: "review this schematic", "check my circuit", "ERC", "floating pins", "unconnected", "any missing footprints", "does this schematic…
Validate a local ZapTrace design with requirements review, ERC/DRC evidence, and bounded engineering risk reports without claiming fabrication approval.