adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help with Vivado design analysis, timing report interpretation, or timing closure. This includes reporttiming interpretation (slack calculation, path analysis, clock skew/uncertainty), reporttimingsummary signoff verification, reportqorassessment (QoR scoring 1-5, assessment…
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help writing XDC/SDC timing or physical constraints for Vivado FPGA designs. This includes clock definitions (createclock, creategeneratedclock, virtual clocks), I/O delay constraints (setinputdelay, setoutputdelay, DDR timing), timing exceptions (setfalsepath, setmulticyclepath…
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help with Vivado in-system debugging, hardware programming, or debug core configuration. This includes ILA (Integrated Logic Analyzer) configuration and trigger strategies, VIO (Virtual I/O) usage for signal monitoring and control, JTAG-to-AXI Master for AXI transaction generation…