Use this skill when the user needs help with Vivado design analysis, timing report interpretation, or timing closure. This includes reporttiming interpretation (slack calculation, path analysis, clock skew/uncertainty), reporttimingsummary signoff verification, reportqorassessment (QoR scoring 1-5, assessment…
Use this skill when the user needs help writing XDC/SDC timing or physical constraints for Vivado FPGA designs. This includes clock definitions (createclock, creategeneratedclock, virtual clocks), I/O delay constraints (setinputdelay, setoutputdelay, DDR timing), timing exceptions (setfalsepath, setmulticyclepath…
Use this skill when the user needs help with Vivado in-system debugging, hardware programming, or debug core configuration. This includes ILA (Integrated Logic Analyzer) configuration and trigger strategies, VIO (Virtual I/O) usage for signal monitoring and control, JTAG-to-AXI Master for AXI transaction generation…
Write and edit executive-level prose in the voice of a senior digital AI consultancy leader who advises C-suite and boards. Use this skill WHENEVER the user asks to write, draft, edit, refine, or generate any piece of professional prose, even if they do not name a style. Triggers include: emails, memos, strategy…
Design, build, and critique data visualizations using Edward Tufte's principles. Use this skill WHENEVER the work involves a chart, graph, plot, dashboard, table, diagram, or any visual display of data, even if the user does not name Tufte or "data viz" explicitly. Triggers include: (1) Building a new chart, graph…