fpga skills

Eriemon/verilog-generator

Skill Codex

Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed…

mapleleavessssssss-wq/vivado-mcp

Skill Claude CodeCodex

A Vivado workflow for reviewing clock-domain crossing, or CDC, reports in FPGA designs. CDC checks whether signals moving between unrelated clock rates are synchronized and transferred safely.

adeleempurpled290/FPGA-Agent-skills

Skill Claude CodeCodex

Use this skill when the user needs help with Vivado in-system debugging, hardware programming, or debug core configuration. This includes ILA (Integrated Logic Analyzer) configuration and trigger strategies, VIO (Virtual I/O) usage for signal monitoring and control, JTAG-to-AXI Master for AXI transaction generation…

Eriemon/hls-generator

Skill Codex

Use when you need to create, write, review, annotate, or validate readable HLS, Vitis HLS, high-level synthesis, or HLS debug workflows.

cobbpeng/fpga-hardware-design-and-review-guide

Skill Claude Code

Comprehensive FPGA hardware design guide based on real-world project experience. Covers pipeline architecture, timing optimization, SystemVerilog coding patterns, CDC handling, and practical debugging techniques. Use this skill when: (1) designing FPGA modules with timing constraints, (2) implementing video processing…