12 tagged fpga, measured the same way as everything else here.
Browse within: accept-language 8cos 8flutter 8gin 8
Skill Claude CodeCodex
Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed…
Skill Claude CodeCodex
Write and check Pyrope (LiveHD's HDL). Use when creating or editing .prp files, translating Verilog to/from Pyrope, or answering Pyrope syntax questions.
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help with Vivado design analysis, timing report interpretation, or timing closure. This includes reporttiming interpretation (slack calculation, path analysis, clock skew/uncertainty), reporttimingsummary signoff verification, reportqorassessment (QoR scoring 1-5, assessment…
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help writing XDC/SDC timing or physical constraints for Vivado FPGA designs. This includes clock definitions (createclock, creategeneratedclock, virtual clocks), I/O delay constraints (setinputdelay, setoutputdelay, DDR timing), timing exceptions (setfalsepath, setmulticyclepath…
adeleempurpled290/FPGA-Agent-skills
Skill Claude CodeCodex
Use this skill when the user needs help with Vivado in-system debugging, hardware programming, or debug core configuration. This includes ILA (Integrated Logic Analyzer) configuration and trigger strategies, VIO (Virtual I/O) usage for signal monitoring and control, JTAG-to-AXI Master for AXI transaction generation…
Skill Claude CodeCodex
Use when you need to create, write, review, annotate, or validate readable HLS, Vitis HLS, high-level synthesis, or HLS debug workflows.
cobbpeng/fpga-hardware-design-and-review-guide
Skill Claude CodeCodex
Comprehensive FPGA hardware design guide based on real-world project experience. Covers pipeline architecture, timing optimization, SystemVerilog coding patterns, CDC handling, and practical debugging techniques. Use this skill when: (1) designing FPGA modules with timing constraints, (2) implementing video processing…